ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays.  The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute.  This is similar to how TBE entries and slots
in output ports are modeled.

1 files changed, 57 insertions, 0 deletions

diff --git a/src/mem/ruby/system/BankedArray.cc b/src/mem/ruby/system/BankedArray.cc
new file mode 100644
index 000000000..3113393a1
--- /dev/null
+++ b/src/mem/ruby/system/BankedArray.cc
@@ -0,0 +1,57 @@
+
+
+#include <vector>
+
+#include "base/intmath.hh"
+#include "mem/ruby/common/TypeDefines.hh"
+#include "mem/ruby/system/BankedArray.hh"
+#include "sim/eventq.hh"
+
+BankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) :
+    EventManager(&mainEventQueue)
+{
+    this->banks = banks;
+    this->accessLatency = accessLatency;
+    this->startIndexBit = startIndexBit;
+
+    if (banks != 0) {
+        bankBits = floorLog2(banks);
+    }
+
+    busyBanks.resize(banks);
+}
+
+bool
+BankedArray::tryAccess(Index idx)
+{
+    if (accessLatency == 0)
+        return true;
+
+    unsigned int bank = mapIndexToBank(idx);
+    assert(bank < banks);
+
+    if (busyBanks[bank].scheduled()) {
+        if (!(busyBanks[bank].startAccess == curTick() && busyBanks[bank].idx == idx)) {
+            return false;
+        } else {
+            return true;  // We tried to allocate resources twice in the same cycle for the same addr
+        }
+    }
+
+    busyBanks[bank].idx = idx;
+    busyBanks[bank].startAccess = curTick();
+
+    // substract 1 so that next cycle the resource available
+    schedule(busyBanks[bank], curTick()+accessLatency-1);
+
+    return true;
+}
+
+unsigned int
+BankedArray::mapIndexToBank(Index idx)
+{
+    if (banks == 1) {
+        return 0;
+    }
+    return idx % banks;
+}