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author | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2012-07-10 22:51:54 -0700 |
commit | 86d6b788f6d7b523c750ffb64d6d8920ec741c49 (patch) | |
tree | 2d6be00e66218b39bae31a27380a47283f70c097 /src/mem/ruby/system/Cache.py | |
parent | 467093ebf238a1954e00576daf14a9f246b51e79 (diff) | |
download | gem5-86d6b788f6d7b523c750ffb64d6d8920ec741c49.tar.xz |
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
Diffstat (limited to 'src/mem/ruby/system/Cache.py')
-rw-r--r-- | src/mem/ruby/system/Cache.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index 79ab9b070..2b4daa68b 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -40,3 +40,9 @@ class RubyCache(SimObject): replacement_policy = Param.String("PSEUDO_LRU", ""); start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line"); is_icache = Param.Bool(False, "is instruction only cache"); + + dataArrayBanks = Param.Int(1, "Number of banks for the data array") + tagArrayBanks = Param.Int(1, "Number of banks for the tag array") + dataAccessLatency = Param.Int(1, "Gem5 cycles for the data array") + tagAccessLatency = Param.Int(1, "Gem5 cycles for the tag array") + resourceStalls = Param.Bool(False, "stall if there is a resource failure") |