diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:19 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:19 -0800 |
commit | ed814899541d65783e93a37ab320650c5075c72d (patch) | |
tree | 4f7b7078d31deb951fa085aa1f20c3ab37ddaf00 /src/mem/ruby/system/CacheMemory.cc | |
parent | 42bebab77973114c5d81a37b50faf521b6f0a029 (diff) | |
download | gem5-ed814899541d65783e93a37ab320650c5075c72d.tar.xz |
ruby: Ruby changes required to use the python config system
This patch includes the necessary changes to connect ruby objects using
the python configuration system. Mainly it consists of removing
unnecessary ruby object pointers and connecting the necessary object
pointers using the generated param objects. This patch includes the
slicc changes necessary to connect generated ruby objects together using
the python configuraiton system.
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.cc')
-rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 35 |
1 files changed, 14 insertions, 21 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 43a0e13e9..11dd8ca96 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -31,9 +31,6 @@ int CacheMemory::m_num_last_level_caches = 0; MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST; -// Output operator declaration -//ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj); - // ******************* Definitions ******************* // Output operator definition @@ -56,29 +53,27 @@ RubyCacheParams::create() CacheMemory::CacheMemory(const Params *p) : SimObject(p) { - int cache_size = p->size; + m_cache_size = p->size; m_latency = p->latency; m_cache_assoc = p->assoc; - string policy = p->replacement_policy; - m_controller = p->controller; - - int num_lines = cache_size/RubySystem::getBlockSizeBytes(); - m_cache_num_sets = num_lines / m_cache_assoc; - m_cache_num_set_bits = log_int(m_cache_num_sets); - assert(m_cache_num_set_bits > 0); - - if(policy == "PSEUDO_LRU") - m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc); - else if (policy == "LRU") - m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc); - else - assert(false); - + m_policy = p->replacement_policy; } void CacheMemory::init() { + m_cache_num_sets = (m_cache_size / m_cache_assoc) / RubySystem::getBlockSizeBytes(); + assert(m_cache_num_sets > 1); + m_cache_num_set_bits = log_int(m_cache_num_sets); + assert(m_cache_num_set_bits > 0); + + if(m_policy == "PSEUDO_LRU") + m_replacementPolicy_ptr = new PseudoLRUPolicy(m_cache_num_sets, m_cache_assoc); + else if (m_policy == "LRU") + m_replacementPolicy_ptr = new LRUPolicy(m_cache_num_sets, m_cache_assoc); + else + assert(false); + m_num_last_level_caches = MachineType_base_count(MachineType_FIRST); #if 0 @@ -126,8 +121,6 @@ CacheMemory::numberOfLastLevelCaches() void CacheMemory::printConfig(ostream& out) { out << "Cache config: " << m_cache_name << endl; - if (m_controller != NULL) - out << " controller: " << m_controller->getName() << endl; out << " cache_associativity: " << m_cache_assoc << endl; out << " num_cache_sets_bits: " << m_cache_num_set_bits << endl; const int cache_num_sets = 1 << m_cache_num_set_bits; |