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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2011-03-19 18:34:59 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2011-03-19 18:34:59 -0500 |
| commit | 611f052e963b06b4a7e02b2fc6d847cd6d08d038 (patch) | |
| tree | 0a3bdb5787d5e6ae9b0e07145cf2d32b4a532d6b /src/mem/ruby/system/CacheMemory.cc | |
| parent | 2f4276448b82b2aa077ae257171b5cb04b7048f6 (diff) | |
| download | gem5-611f052e963b06b4a7e02b2fc6d847cd6d08d038.tar.xz | |
Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.cc')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 7fcb5431b..ea5054e4c 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -159,7 +159,7 @@ CacheMemory::findTagInSetIgnorePermissions(Index cacheSet, } bool -CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, +CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) { assert(address == line_address(address)); @@ -177,7 +177,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, return true; } if ((entry->m_Permission == AccessPermission_Read_Only) && - (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) { + (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) { return true; } // The line must not be accessible @@ -187,7 +187,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type, } bool -CacheMemory::testCacheAccess(const Address& address, CacheRequestType type, +CacheMemory::testCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr) { assert(address == line_address(address)); @@ -367,18 +367,18 @@ CacheMemory::recordCacheContents(CacheRecorder& tr) const for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { AccessPermission perm = m_cache[i][j]->m_Permission; - CacheRequestType request_type = CacheRequestType_NULL; + RubyRequestType request_type = RubyRequestType_NULL; if (perm == AccessPermission_Read_Only) { if (m_is_instruction_only_cache) { - request_type = CacheRequestType_IFETCH; + request_type = RubyRequestType_IFETCH; } else { - request_type = CacheRequestType_LD; + request_type = RubyRequestType_LD; } } else if (perm == AccessPermission_Read_Write) { - request_type = CacheRequestType_ST; + request_type = RubyRequestType_ST; } - if (request_type != CacheRequestType_NULL) { + if (request_type != RubyRequestType_NULL) { #if 0 tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address, Address(0), request_type, |