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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-01-29 20:29:17 -0800
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-01-29 20:29:17 -0800
commit98c94cfe3ce83634f3bad79ca18263f42e36ca6a (patch)
treeb299448162932c5574b87238a3b02a01efd14db6 /src/mem/ruby/system/CacheMemory.cc
parentb43994ba45b7805da0d1d9600e5cbb8332057403 (diff)
downloadgem5-98c94cfe3ce83634f3bad79ca18263f42e36ca6a.tar.xz
ruby: Convert most Ruby objects to M5 SimObjects.
The necessary companion conversion of Ruby objects generated by SLICC are converted to M5 SimObjects in the following patch, so this patch alone does not compile. Conversion of Garnet network models is also handled in a separate patch; that code is temporarily disabled from compiling to allow testing of interim code.
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.cc')
-rw-r--r--src/mem/ruby/system/CacheMemory.cc59
1 files changed, 28 insertions, 31 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index cf3e094ad..43a0e13e9 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -47,41 +47,20 @@ ostream& operator<<(ostream& out, const CacheMemory& obj)
// ****************************************************************
-CacheMemory::CacheMemory(const string & name)
- : m_cache_name(name)
+CacheMemory *
+RubyCacheParams::create()
{
- m_profiler_ptr = new CacheProfiler(name);
+ return new CacheMemory(this);
}
-void CacheMemory::init(const vector<string> & argv)
+CacheMemory::CacheMemory(const Params *p)
+ : SimObject(p)
{
- int cache_size = -1;
- string policy;
-
- m_num_last_level_caches =
- MachineType_base_count(MachineType_FIRST);
- m_controller = NULL;
- for (uint32 i=0; i<argv.size(); i+=2) {
- if (argv[i] == "size") {
- cache_size = atoi(argv[i+1].c_str());
- } else if (argv[i] == "latency") {
- m_latency = atoi(argv[i+1].c_str());
- } else if (argv[i] == "assoc") {
- m_cache_assoc = atoi(argv[i+1].c_str());
- } else if (argv[i] == "replacement_policy") {
- policy = argv[i+1];
- } else if (argv[i] == "controller") {
- m_controller = RubySystem::getController(argv[i+1]);
- if (m_last_level_machine_type < m_controller->getMachineType()) {
- m_num_last_level_caches =
- MachineType_base_count(m_controller->getMachineType());
- m_last_level_machine_type =
- m_controller->getMachineType();
- }
- } else {
- cerr << "WARNING: CacheMemory: Unknown configuration parameter: " << argv[i] << endl;
- }
- }
+ int cache_size = p->size;
+ m_latency = p->latency;
+ m_cache_assoc = p->assoc;
+ string policy = p->replacement_policy;
+ m_controller = p->controller;
int num_lines = cache_size/RubySystem::getBlockSizeBytes();
m_cache_num_sets = num_lines / m_cache_assoc;
@@ -95,6 +74,24 @@ void CacheMemory::init(const vector<string> & argv)
else
assert(false);
+}
+
+
+void CacheMemory::init()
+{
+ m_num_last_level_caches =
+ MachineType_base_count(MachineType_FIRST);
+#if 0
+ for (uint32 i=0; i<argv.size(); i+=2) {
+ if (m_last_level_machine_type < m_controller->getMachineType()) {
+ m_num_last_level_caches =
+ MachineType_base_count(m_controller->getMachineType());
+ m_last_level_machine_type =
+ m_controller->getMachineType();
+ }
+ }
+#endif
+
m_cache.setSize(m_cache_num_sets);
m_locked.setSize(m_cache_num_sets);
for (int i = 0; i < m_cache_num_sets; i++) {