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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:12 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-08-20 11:46:12 -0700
commit54d76f0ce5d721ad3b4de168db98054844e634cc (patch)
tree19b74bf031e5aa9ecae18b7a1a0d36b5e0fc466c /src/mem/ruby/system/CacheMemory.cc
parenta3b4b9b3e3f8a1462b34d758199312d33af4b0c7 (diff)
downloadgem5-54d76f0ce5d721ad3b4de168db98054844e634cc.tar.xz
ruby: Fixed L2 cache miss profiling
Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.cc')
-rw-r--r--src/mem/ruby/system/CacheMemory.cc15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index c9de85961..9102d1963 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -375,8 +375,19 @@ CacheMemory::setMRU(const Address& address)
void
CacheMemory::profileMiss(const CacheMsg& msg)
{
- m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(),
- msg.getSize(), msg.getPrefetch());
+ m_profiler_ptr->addCacheStatSample(msg.getType(),
+ msg.getAccessMode(),
+ msg.getPrefetch());
+}
+
+void
+CacheMemory::profileGenericRequest(GenericRequestType requestType,
+ AccessModeType accessType,
+ PrefetchBit pfBit)
+{
+ m_profiler_ptr->addGenericStatSample(requestType,
+ accessType,
+ pfBit);
}
void