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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 54d76f0ce5d721ad3b4de168db98054844e634cc (patch) | |
| tree | 19b74bf031e5aa9ecae18b7a1a0d36b5e0fc466c /src/mem/ruby/system/CacheMemory.hh | |
| parent | a3b4b9b3e3f8a1462b34d758199312d33af4b0c7 (diff) | |
| download | gem5-54d76f0ce5d721ad3b4de168db98054844e634cc.tar.xz | |
ruby: Fixed L2 cache miss profiling
Fixed L2 cache miss profiling for the MOESI_CMP_token protocol
Diffstat (limited to 'src/mem/ruby/system/CacheMemory.hh')
| -rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index f004b8310..c1d49f784 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -37,6 +37,7 @@ #include "mem/protocol/AccessPermission.hh" #include "mem/protocol/CacheMsg.hh" #include "mem/protocol/CacheRequestType.hh" +#include "mem/protocol/GenericRequestType.hh" #include "mem/protocol/MachineType.hh" #include "mem/ruby/common/Address.hh" #include "mem/ruby/common/DataBlock.hh" @@ -112,6 +113,10 @@ class CacheMemory : public SimObject void profileMiss(const CacheMsg & msg); + void profileGenericRequest(GenericRequestType requestType, + AccessModeType accessType, + PrefetchBit pfBit); + void getMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes); void setMemoryValue(const Address& addr, char* value, |