ruby: add stats to .sm files, remove cache profiler

This patch changes the way cache statistics are collected in ruby.

As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.

Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.

--HG--
rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py

1 files changed, 15 insertions, 16 deletions

diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 8aca250b3..db9e00e21 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -36,10 +36,8 @@
 #include "base/statistics.hh"
 #include "mem/protocol/CacheResourceType.hh"
 #include "mem/protocol/CacheRequestType.hh"
-#include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/DataBlock.hh"
-#include "mem/ruby/profiler/CacheProfiler.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
@@ -100,34 +98,37 @@ class CacheMemory : public SimObject
     // Set this address to most recently used
     void setMRU(const Address& address);
 
-    void profileMiss(const RubyRequest & msg);
-
-    void profileGenericRequest(GenericRequestType requestType,
-                               RubyAccessMode accessType,
-                               PrefetchBit pfBit);
-
     void setLocked (const Address& addr, int context);
     void clearLocked (const Address& addr);
     bool isLocked (const Address& addr, int context);
+
     // Print cache contents
     void print(std::ostream& out) const;
     void printData(std::ostream& out) const;
 
-    void clearStats() const;
-    void printStats(std::ostream& out) const;
-
-    void recordRequestType(CacheRequestType requestType);
     void regStats();
+    bool checkResourceAvailable(CacheResourceType res, Address addr);
+    void recordRequestType(CacheRequestType requestType);
+
+  public:
+    Stats::Scalar m_demand_hits;
+    Stats::Scalar m_demand_misses;
+    Stats::Formula m_demand_accesses;
+
+    Stats::Scalar m_sw_prefetches;
+    Stats::Scalar m_hw_prefetches;
+    Stats::Formula m_prefetches;
+
+    Stats::Vector m_accessModeType;
 
     Stats::Scalar numDataArrayReads;
     Stats::Scalar numDataArrayWrites;
     Stats::Scalar numTagArrayReads;
     Stats::Scalar numTagArrayWrites;
 
-    bool checkResourceAvailable(CacheResourceType res, Address addr);
-
     Stats::Scalar numTagArrayStalls;
     Stats::Scalar numDataArrayStalls;
+
   private:
     // convert a Address to its location in the cache
     Index addressToCacheSet(const Address& address) const;
@@ -156,8 +157,6 @@ class CacheMemory : public SimObject
 
     AbstractReplacementPolicy *m_replacementPolicy_ptr;
 
-    CacheProfiler* m_profiler_ptr;
-
     BankedArray dataArray;
     BankedArray tagArray;