ruby: banked cache array resource model

This patch models a cache as separate tag and data arrays.  The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute.  This is similar to how TBE entries and slots
in output ports are modeled.

1 files changed, 10 insertions, 0 deletions

diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 53cd6b286..ee3c1a7fc 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -35,6 +35,7 @@
 
 #include "base/hashmap.hh"
 #include "base/statistics.hh"
+#include "mem/protocol/CacheResourceType.hh"
 #include "mem/protocol/CacheRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/RubyRequest.hh"
@@ -43,6 +44,7 @@
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
+#include "mem/ruby/system/BankedArray.hh"
 #include "mem/ruby/system/LRUPolicy.hh"
 #include "mem/ruby/system/PseudoLRUPolicy.hh"
 #include "params/RubyCache.hh"
@@ -125,6 +127,10 @@ class CacheMemory : public SimObject
     Stats::Scalar numTagArrayReads;
     Stats::Scalar numTagArrayWrites;
 
+    bool checkResourceAvailable(CacheResourceType res, Address addr);
+
+    Stats::Scalar numTagArrayStalls;
+    Stats::Scalar numDataArrayStalls;
   private:
     // convert a Address to its location in the cache
     Index addressToCacheSet(const Address& address) const;
@@ -155,12 +161,16 @@ class CacheMemory : public SimObject
 
     CacheProfiler* m_profiler_ptr;
 
+    BankedArray dataArray;
+    BankedArray tagArray;
+
     int m_cache_size;
     std::string m_policy;
     int m_cache_num_sets;
     int m_cache_num_set_bits;
     int m_cache_assoc;
     int m_start_index_bit;
+    bool m_resource_stalls;
 };
 
 #endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__