mem: Make cache terminology easier to understand

This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.

1 files changed, 3 insertions, 2 deletions

diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 3c895e627..2b65d675a 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -89,8 +89,9 @@ DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
             pkt->getAddr(), id);
     DMASequencer *seq = static_cast<DMASequencer *>(&owner);
 
-    if (pkt->memInhibitAsserted())
-        panic("DMASequencer should never see an inhibited request\n");
+    if (pkt->cacheResponding())
+        panic("DMASequencer should never see a request with the "
+              "cacheResponding flag set\n");
 
     assert(isPhysMemAddress(pkt->getAddr()));
     assert(getOffset(pkt->getAddr()) + pkt->getSize() <=