summaryrefslogtreecommitdiff
path: root/src/mem/ruby/system/DMASequencer.cc
diff options
context:
space:
mode:
authorNilay Vaish <nilay@cs.wisc.edu>2011-03-22 06:41:54 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2011-03-22 06:41:54 -0500
commit1764ebbf30cfd94eb7ccc618ade0d70049db000e (patch)
tree3c400317f716fcf50c996e9f4fb03980efd9cf3a /src/mem/ruby/system/DMASequencer.cc
parent46cce440be4999cfdedebbf190c83570ba9f1b49 (diff)
downloadgem5-1764ebbf30cfd94eb7ccc618ade0d70049db000e.tar.xz
Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use in coherence protocols. In place of CacheMsg, the RubyRequest class will used. This class is already present in slicc_interface/RubyRequest.hh. In fact, objects of class CacheMsg are generated by copying values from a RubyRequest object.
Diffstat (limited to 'src/mem/ruby/system/DMASequencer.cc')
-rw-r--r--src/mem/ruby/system/DMASequencer.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 772bc5142..2889c0c57 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -53,11 +53,11 @@ DMASequencer::makeRequest(const RubyRequest &request)
return RequestStatus_BufferFull;
}
- uint64_t paddr = request.paddr;
+ uint64_t paddr = request.m_PhysicalAddress.getAddress();
uint8_t* data = request.data;
- int len = request.len;
+ int len = request.m_Size;
bool write = false;
- switch(request.type) {
+ switch(request.m_Type) {
case RubyRequestType_LD:
write = false;
break;