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authorJason Power <power.jg@gmail.com>2015-02-26 09:58:26 -0600
committerJason Power <power.jg@gmail.com>2015-02-26 09:58:26 -0600
commit670f44e05eb8eb1a56b36c4390cf83807a28d823 (patch)
treea050dd6f28aebe5221bcf109c2dadb085ad1a67c /src/mem/ruby/system/DMASequencer.cc
parentf18d2120fa66803912dcce61fe6c704a6a05a2d1 (diff)
downloadgem5-670f44e05eb8eb1a56b36c4390cf83807a28d823.tar.xz
Ruby: Update backing store option to propagate through to all RubyPorts
Previously, the user would have to manually set access_backing_store=True on all RubyPorts (Sequencers) in the config files. Now, instead there is one global option that each RubyPort checks on initialization. Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/ruby/system/DMASequencer.cc')
-rw-r--r--src/mem/ruby/system/DMASequencer.cc17
1 files changed, 13 insertions, 4 deletions
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 2c4c024b6..47a9b13aa 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -40,7 +40,8 @@
DMASequencer::DMASequencer(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
- slave_port(csprintf("%s.slave", name()), this, 0),
+ slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system,
+ p->ruby_system->getAccessBackingStore()),
drainManager(NULL), system(p->system), retry(false)
{
assert(m_version != -1);
@@ -73,8 +74,10 @@ DMASequencer::getSlavePort(const std::string &if_name, PortID idx)
}
DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
- DMASequencer *_port, PortID id)
- : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this)
+ DMASequencer *_port, PortID id, RubySystem* _ruby_system,
+ bool _access_backing_store)
+ : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
+ ruby_system(_ruby_system), access_backing_store(_access_backing_store)
{
DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
}
@@ -208,8 +211,14 @@ DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt)
DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
// turn packet around to go back to requester if response expected
- if (needsResponse) {
+
+ if (access_backing_store) {
+ ruby_system->getPhysMem()->access(pkt);
+ } else if (needsResponse) {
pkt->makeResponse();
+ }
+
+ if (needsResponse) {
DPRINTF(RubyDma, "Sending packet back over port\n");
// send next cycle
schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());