ruby: Convert most Ruby objects to M5 SimObjects.

The necessary companion conversion of Ruby objects generated by SLICC
are converted to M5 SimObjects in the following patch, so this patch
alone does not compile.
Conversion of Garnet network models is also handled in a separate
patch; that code is temporarily disabled from compiling to allow
testing of interim code.

1 files changed, 5 insertions, 8 deletions

diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 77c0a2258..12a5c790f 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -6,6 +6,8 @@
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/system/RubyPort.hh"
 
+#include "params/DMASequencer.hh"
+
 struct DMARequest {
   uint64_t start_paddr;
   int len;
@@ -16,13 +18,11 @@ struct DMARequest {
   int64_t id;
 };
 
-class MessageBuffer;
-class AbstractController;
-
 class DMASequencer :public RubyPort {
 public:
-  DMASequencer(const string & name);
-  void init(const vector<string> & argv);
+    typedef DMASequencerParams Params;
+  DMASequencer(const Params *);
+  void init();
   /* external interface */
   int64_t makeRequest(const RubyRequest & request);
   bool isReady(const RubyRequest & request, bool dont_set = false) { assert(0); return false;};
@@ -39,13 +39,10 @@ private:
   void issueNext();
 
 private:
-  int m_version;
-  AbstractController* m_controller;
   bool m_is_busy;
   uint64_t m_data_block_mask;
   DMARequest active_request;
   int num_active_requests;
-  MessageBuffer* m_mandatory_q_ptr;
 };
 
 #endif // DMACONTROLLER_H