m5merge(2): another merge of regression stats

1 files changed, 32 insertions, 30 deletions

diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 24129526a..61d7ef1c6 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -26,48 +26,50 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef DMASEQUENCER_H
-#define DMASEQUENCER_H
+#ifndef __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
+#define __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__
 
 #include <ostream>
+
 #include "mem/ruby/common/DataBlock.hh"
 #include "mem/ruby/system/RubyPort.hh"
-
 #include "params/DMASequencer.hh"
 
-struct DMARequest {
-  uint64_t start_paddr;
-  int len;
-  bool write;
-  int bytes_completed;
-  int bytes_issued;
-  uint8* data;
-  PacketPtr pkt;
+struct DMARequest
+{
+    uint64_t start_paddr;
+    int len;
+    bool write;
+    int bytes_completed;
+    int bytes_issued;
+    uint8* data;
+    PacketPtr pkt;
 };
 
-class DMASequencer :public RubyPort {
-public:
+class DMASequencer : public RubyPort
+{
+  public:
     typedef DMASequencerParams Params;
-  DMASequencer(const Params *);
-  void init();
-  /* external interface */
-  RequestStatus makeRequest(const RubyRequest & request);
-  bool busy() { return m_is_busy;}
+    DMASequencer(const Params *);
+    void init();
+    /* external interface */
+    RequestStatus makeRequest(const RubyRequest & request);
+    bool busy() { return m_is_busy;}
 
-  /* SLICC callback */
-  void dataCallback(const DataBlock & dblk);
-  void ackCallback();
+    /* SLICC callback */
+    void dataCallback(const DataBlock & dblk);
+    void ackCallback();
 
-  void printConfig(std::ostream & out);
+    void printConfig(std::ostream & out);
 
-private:
-  void issueNext();
+  private:
+    void issueNext();
 
-private:
-  bool m_is_busy;
-  uint64_t m_data_block_mask;
-  DMARequest active_request;
-  int num_active_requests;
+  private:
+    bool m_is_busy;
+    uint64_t m_data_block_mask;
+    DMARequest active_request;
+    int num_active_requests;
 };
 
-#endif // DMACONTROLLER_H
+#endif // __MEM_RUBY_SYSTEM_DMASEQUENCER_HH__