slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate.  They are:

1.  Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller.  I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2.  DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well.  It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc.  Currently, only int parameters are supported.

1 files changed, 3 insertions, 3 deletions

diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 6445ecc62..39de679ed 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -59,7 +59,7 @@ public:
   int mapAddressToLocalIdx(PhysAddress address);
   static int mapAddressToDirectoryVersion(PhysAddress address);
 
-  int getSize() { return m_size_bytes; }
+  uint64 getSize() { return m_size_bytes; }
 
   // Public Methods
   void printConfig(ostream& out) const;
@@ -84,8 +84,8 @@ private:
   // Data Members (m_ prefix)
   Directory_Entry **m_entries;
   //  int m_size;  // # of memory module blocks this directory is responsible for
-  uint32 m_size_bytes;
-  uint32 m_size_bits;
+  uint64 m_size_bytes;
+  uint64 m_size_bits;
   int m_num_entries;
   int m_version;