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author | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
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committer | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
commit | 1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6 (patch) | |
tree | f804e0cbaae1e2bf7b0037e1b88851c2b64dfd60 /src/mem/ruby/system/MemoryControl.py | |
parent | 4a52a6ea2d84933a1ac8418fe2ba9222832a690d (diff) | |
download | gem5-1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6.tar.xz |
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Diffstat (limited to 'src/mem/ruby/system/MemoryControl.py')
-rw-r--r-- | src/mem/ruby/system/MemoryControl.py | 22 |
1 files changed, 4 insertions, 18 deletions
diff --git a/src/mem/ruby/system/MemoryControl.py b/src/mem/ruby/system/MemoryControl.py index 8144e70fc..dafd0a789 100644 --- a/src/mem/ruby/system/MemoryControl.py +++ b/src/mem/ruby/system/MemoryControl.py @@ -30,24 +30,10 @@ from m5.params import * from m5.SimObject import SimObject -class RubyMemoryControl(SimObject): - type = 'RubyMemoryControl' +class MemoryControl(SimObject): + abstract = True + type = 'MemoryControl' cxx_class = 'MemoryControl' version = Param.Int(""); + mem_bus_cycle_multiplier = Param.Int(10, ""); - banks_per_rank = Param.Int(8, ""); - ranks_per_dimm = Param.Int(2, ""); - dimms_per_channel = Param.Int(2, ""); - bank_bit_0 = Param.Int(8, ""); - rank_bit_0 = Param.Int(11, ""); - dimm_bit_0 = Param.Int(12, ""); - bank_queue_size = Param.Int(12, ""); - bank_busy_time = Param.Int(11, ""); - rank_rank_delay = Param.Int(1, ""); - read_write_delay = Param.Int(2, ""); - basic_bus_busy_time = Param.Int(2, ""); - mem_ctl_latency = Param.Int(12, ""); - refresh_period = Param.Int(1560, ""); - tFaw = Param.Int(0, ""); - mem_random_arbitrate = Param.Int(0, ""); - mem_fixed_delay = Param.Int(0, ""); |