summaryrefslogtreecommitdiff
path: root/src/mem/ruby/system/PerfectCacheMemory.hh
diff options
context:
space:
mode:
authorDerek Hower <drh5@cs.wisc.edu>2009-08-05 14:23:32 -0500
committerDerek Hower <drh5@cs.wisc.edu>2009-08-05 14:23:32 -0500
commitdff7c9eaa0795dc23b32608dc1e26026a5292d30 (patch)
treef5335c8359d19535c6832238dd51d528ba6c1086 /src/mem/ruby/system/PerfectCacheMemory.hh
parent60d4a0f6d7328b251797b14c33fd6766b95bc1ea (diff)
parent867269bc9650e0b5b2384daf0c09fba60aa7438c (diff)
downloadgem5-dff7c9eaa0795dc23b32608dc1e26026a5292d30.tar.xz
merge
Diffstat (limited to 'src/mem/ruby/system/PerfectCacheMemory.hh')
-rw-r--r--src/mem/ruby/system/PerfectCacheMemory.hh14
1 files changed, 9 insertions, 5 deletions
diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh
index 90c9273e5..6561d028b 100644
--- a/src/mem/ruby/system/PerfectCacheMemory.hh
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh
@@ -43,7 +43,6 @@
#include "mem/gems_common/Map.hh"
#include "mem/protocol/AccessPermission.hh"
#include "mem/ruby/common/Address.hh"
-#include "mem/ruby/slicc_interface/AbstractChip.hh"
template<class ENTRY>
class PerfectCacheLineState {
@@ -54,11 +53,18 @@ public:
};
template<class ENTRY>
+extern inline
+ostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
+{
+ return out;
+}
+
+template<class ENTRY>
class PerfectCacheMemory {
public:
// Constructors
- PerfectCacheMemory(AbstractChip* chip_ptr);
+ PerfectCacheMemory();
// Destructor
//~PerfectCacheMemory();
@@ -106,7 +112,6 @@ private:
// Data Members (m_prefix)
Map<Address, PerfectCacheLineState<ENTRY> > m_map;
- AbstractChip* m_chip_ptr;
};
// Output operator declaration
@@ -129,9 +134,8 @@ ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
template<class ENTRY>
extern inline
-PerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr)
+PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
{
- m_chip_ptr = chip_ptr;
}
// STATIC METHODS