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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-09 07:29:59 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-09 07:29:59 -0500 |
commit | f59a7af50a7309944abfe1997057f52591619635 (patch) | |
tree | 4daa578b6ba1664152da4412786317bce26ff0ee /src/mem/ruby/system/RubyMemoryControl.hh | |
parent | 38736ce7c33d7b1bf1e982f5d8cacd13908a32f4 (diff) | |
download | gem5-f59a7af50a7309944abfe1997057f52591619635.tar.xz |
ruby: stats: use gem5's stats for cache and memory controllers
This moves event and transition count statistics for cache controllers to
gem5's statistics. It does the same for the statistics associated with the
memory controller in ruby.
All the cache/directory/dma controllers individually collect the event and
transition counts. A callback function, collateStats(), has been added that
is invoked on the controller version 0 of each controller class. This
function adds all the individual controller statistics to a vector
variables. All the code for registering the statistical variables and
collating them is generated by SLICC. The patch removes the files
*_Profiler.{cc,hh} and *_ProfileDumper.{cc,hh} which were earlier used for
collecting and dumping statistics respectively.
Diffstat (limited to 'src/mem/ruby/system/RubyMemoryControl.hh')
-rw-r--r-- | src/mem/ruby/system/RubyMemoryControl.hh | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mem/ruby/system/RubyMemoryControl.hh b/src/mem/ruby/system/RubyMemoryControl.hh index d0dfa5b8d..7be74583a 100644 --- a/src/mem/ruby/system/RubyMemoryControl.hh +++ b/src/mem/ruby/system/RubyMemoryControl.hh @@ -81,8 +81,7 @@ class RubyMemoryControl : public MemoryControl bool areNSlotsAvailable(int n) { return true; }; // infinite queue length void print(std::ostream& out) const; - void clearStats() const; - void printStats(std::ostream& out) const; + void regStats(); const int getBank(const physical_address_t addr) const; const int getRank(const physical_address_t addr) const; |