diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
commit | 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 (patch) | |
tree | 61ca1dcb9336bc1f4dbc791c876875c1c260ca8d /src/mem/ruby/system/RubyPort.cc | |
parent | 9baa35ba802f2cfb9fb9ecdebf111f4cd793a428 (diff) | |
download | gem5-2a740aa09682c32eb8f1f8880f279c943d8c6ee1.tar.xz |
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
Diffstat (limited to 'src/mem/ruby/system/RubyPort.cc')
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index dcedc7841..1259f0f15 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -78,8 +78,8 @@ RubyPort::init() m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -MasterPort & -RubyPort::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyPort::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "pio_port") { return pio_port; @@ -91,7 +91,7 @@ RubyPort::getMasterPort(const std::string &if_name, int idx) // pass it along to our super class return MemObject::getMasterPort(if_name, idx); } else { - if (idx >= static_cast<int>(master_ports.size())) { + if (idx >= static_cast<PortID>(master_ports.size())) { panic("RubyPort::getMasterPort: unknown index %d\n", idx); } @@ -99,8 +99,8 @@ RubyPort::getMasterPort(const std::string &if_name, int idx) } } -SlavePort & -RubyPort::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +RubyPort::getSlavePort(const std::string &if_name, PortID idx) { // used by the CPUs to connect the caches to the interconnect, and // for the x86 case also the interrupt master @@ -108,7 +108,7 @@ RubyPort::getSlavePort(const std::string &if_name, int idx) // pass it along to our super class return MemObject::getSlavePort(if_name, idx); } else { - if (idx >= static_cast<int>(slave_ports.size())) { + if (idx >= static_cast<PortID>(slave_ports.size())) { panic("RubyPort::getSlavePort: unknown index %d\n", idx); } |