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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-30 09:42:36 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-03-30 09:42:36 -0400 |
commit | a128ba7cd1ab506e3468c82c1060a7fb4ad909b1 (patch) | |
tree | 626dc6046e0c8edb99a7f7a9db4c8ef7d8664636 /src/mem/ruby/system/RubyPort.cc | |
parent | f9d403a7b95c50a8b75f8442101eb87ca465f967 (diff) | |
download | gem5-a128ba7cd1ab506e3468c82c1060a7fb4ad909b1.tar.xz |
Ruby: Remove the physMemPort and instead access memory directly
This patch removes the physMemPort from the RubySequencer and instead
uses the system pointer to access the physmem. The system already
keeps track of the physmem and the valid memory address ranges, and
with this patch we merely make use of that existing functionality. The
memory is modified so that it is possible to call the access functions
(atomic and functional) without going through the port, and the memory
is allowed to be unconnected, i.e. have no ports (since Ruby does not
attach it like the conventional memory system).
Diffstat (limited to 'src/mem/ruby/system/RubyPort.cc')
-rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 29 |
1 files changed, 5 insertions, 24 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index 1769c51fd..8fd68be7c 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -45,14 +45,14 @@ #include "mem/protocol/AccessPermission.hh" #include "mem/ruby/slicc_interface/AbstractController.hh" #include "mem/ruby/system/RubyPort.hh" +#include "sim/system.hh" RubyPort::RubyPort(const Params *p) : MemObject(p), m_version(p->version), m_controller(NULL), m_mandatory_q_ptr(NULL), pio_port(csprintf("%s-pio-port", name()), this), m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), - physMemPort(csprintf("%s-physMemPort", name()), this), - drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system), + drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) { assert(m_version != -1); @@ -84,10 +84,6 @@ RubyPort::getMasterPort(const std::string &if_name, int idx) return pio_port; } - if (if_name == "physMemPort") { - return physMemPort; - } - // used by the x86 CPUs to connect the interrupt PIO and interrupt slave // port if (if_name != "master") { @@ -471,7 +467,7 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt) // The following command performs the real functional access. // This line should be removed once Ruby supplies the official version // of data. - ruby_port->physMemPort.sendFunctional(pkt); + ruby_port->system->physmem->doFunctionalAccess(pkt); } // turn packet around to go back to requester if response expected @@ -568,10 +564,6 @@ RubyPort::getDrainCount(Event *de) count += pio_port.drain(de); DPRINTF(Config, "count after pio check %d\n", count); } - if (physMemPort.isConnected()) { - count += physMemPort.drain(de); - DPRINTF(Config, "count after physmem check %d\n", count); - } for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { count += (*p)->drain(de); @@ -654,7 +646,7 @@ RubyPort::M5Port::hitCallback(PacketPtr pkt) DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); if (accessPhysMem) { - ruby_port->physMemPort.sendAtomic(pkt); + ruby_port->system->physmem->doAtomicAccess(pkt); } else if (needsResponse) { pkt->makeResponse(); } @@ -696,18 +688,7 @@ RubyPort::M5Port::getAddrRanges() bool RubyPort::M5Port::isPhysMemAddress(Addr addr) { - AddrRangeList physMemAddrList = - ruby_port->physMemPort.getSlavePort().getAddrRanges(); - for (AddrRangeIter iter = physMemAddrList.begin(); - iter != physMemAddrList.end(); - iter++) { - if (addr >= iter->start && addr <= iter->end) { - DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", - iter->start, iter->end); - return true; - } - } - return false; + return ruby_port->system->isMemory(addr); } unsigned |