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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-23 11:07:14 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-01-23 11:07:14 -0600 |
| commit | 63563c9df2eca46231768a448e981e8bb7856655 (patch) | |
| tree | d45aaa1decb0d9dba3ccd01d7ecb31804d85f1f8 /src/mem/ruby/system/RubyPort.hh | |
| parent | 9481d05b8aea0faf336f604f3e18b451d5197c12 (diff) | |
| download | gem5-63563c9df2eca46231768a448e981e8bb7856655.tar.xz | |
O3, Ruby: Forward invalidations from Ruby to O3 CPU
This patch implements the functionality for forwarding invalidations and
replacements from the L1 cache of the Ruby memory system to the O3 CPU. The
implementation adds a list of ports to RubyPort. Whenever a replacement or an
invalidation is performed, the L1 cache forwards this to all the ports, which
is the LSQ in case of the O3 CPU.
Diffstat (limited to 'src/mem/ruby/system/RubyPort.hh')
| -rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index d8dbe0cda..2ffdef3d9 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2009 Advanced Micro Devices, Inc. + * Copyright (c) 2011 Mark D. Hill and David A. Wood * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -58,6 +59,7 @@ class RubyPort : public MemObject RubySystem*_system, bool _access_phys_mem); bool sendTiming(PacketPtr pkt); void hitCallback(PacketPtr pkt); + void evictionCallback(const Address& address); unsigned deviceBlockSize() const; bool onRetryList() @@ -129,8 +131,8 @@ class RubyPort : public MemObject protected: const std::string m_name; void ruby_hit_callback(PacketPtr pkt); - void hit(PacketPtr pkt); void testDrainComplete(); + void ruby_eviction_callback(const Address& address); int m_version; AbstractController* m_controller; |