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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:44 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-16 05:49:44 -0400 |
| commit | 247586274724ea9f2a22a87747c9e074870d16a8 (patch) | |
| tree | 0de83b50fe2856e3bc43eb9a24e2f767719ee2d5 /src/mem/ruby/system/RubyPort.hh | |
| parent | df973abef3a70074971375cfe52c46f53528c00e (diff) | |
| download | gem5-247586274724ea9f2a22a87747c9e074870d16a8.tar.xz | |
arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.
--HG--
rename : src/arch/x86/insts/microldstop.hh => src/arch/x86/ldstflags.hh
Diffstat (limited to 'src/mem/ruby/system/RubyPort.hh')
| -rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 12e97208f..648580246 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -182,6 +182,7 @@ class RubyPort : public MemObject AbstractController* m_controller; MessageBuffer* m_mandatory_q_ptr; bool m_usingRubyTester; + System* system; private: void addToRetryList(MemSlavePort * port) @@ -205,7 +206,6 @@ class RubyPort : public MemObject std::vector<PioMasterPort *> master_ports; DrainManager *drainManager; - System* system; // // Based on similar code in the M5 bus. Stores pointers to those ports |