MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

1 files changed, 20 insertions, 5 deletions

diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index bef291d63..d97f6e69e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -1,4 +1,16 @@
 /*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
  * Copyright (c) 2009 Advanced Micro Devices, Inc.
  * Copyright (c) 2011 Mark D. Hill and David A. Wood
  * All rights reserved.
@@ -46,7 +58,7 @@ class AbstractController;
 class RubyPort : public MemObject
 {
   public:
-    class M5Port : public QueuedPort
+    class M5Port : public QueuedSlavePort
     {
       private:
 
@@ -74,6 +86,7 @@ class RubyPort : public MemObject
         virtual bool recvTiming(PacketPtr pkt);
         virtual Tick recvAtomic(PacketPtr pkt);
         virtual void recvFunctional(PacketPtr pkt);
+        virtual AddrRangeList getAddrRanges();
 
       private:
         bool isPhysMemAddress(Addr addr);
@@ -83,7 +96,7 @@ class RubyPort : public MemObject
 
     friend class M5Port;
 
-    class PioPort : public QueuedPort
+    class PioPort : public QueuedMasterPort
     {
       private:
 
@@ -119,7 +132,8 @@ class RubyPort : public MemObject
 
     void init();
 
-    Port *getPort(const std::string &if_name, int idx);
+    MasterPort &getMasterPort(const std::string &if_name, int idx);
+    SlavePort &getSlavePort(const std::string &if_name, int idx);
 
     virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
     virtual int outstandingCount() const = 0;
@@ -163,9 +177,10 @@ class RubyPort : public MemObject
 
     PioPort physMemPort;
 
-    /*! Vector of CPU Port attached to this Ruby port. */
+    /** Vector of M5 Ports attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;
-    std::vector<M5Port*> cpu_ports;
+    std::vector<M5Port*> slave_ports;
+    std::vector<PioPort*> master_ports;
 
     Event *drainEvent;