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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:11:55 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:11:55 -0500 |
| commit | 92585d60c9c5c34272cb356362bab638d15bcac0 (patch) | |
| tree | c82ee2c48925353ce37d2d973fb95cabf703f0f1 /src/mem/ruby/system/RubyPortProxy.hh | |
| parent | e76442e203bd4ce18e897658a17756a3d00bdeb8 (diff) | |
| download | gem5-92585d60c9c5c34272cb356362bab638d15bcac0.tar.xz | |
mem: Move DRAM interleaving check to init
This patch fixes a bug where the DRAM controller tried to access the
system cacheline size before the system pointer was initialised. It
also fixes a bug where the granularity is 0 (no interleaving).
Diffstat (limited to 'src/mem/ruby/system/RubyPortProxy.hh')
0 files changed, 0 insertions, 0 deletions