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authorAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
committerAkash Bagdia <akash.bagdia@arm.com>2013-06-27 05:49:49 -0400
commit7eccb1b779cb6458ed78ba73f2fdabe94fa805b3 (patch)
treea47dc043defd5ff0afad3bdf103bc1a147dc0091 /src/mem/ruby/system/RubySystem.py
parentf821c5472b5e524053846bd57b83c81238be159f (diff)
downloadgem5-7eccb1b779cb6458ed78ba73f2fdabe94fa805b3.tar.xz
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour. The main motivation for these simplifications is to ease the introduction of clock domains.
Diffstat (limited to 'src/mem/ruby/system/RubySystem.py')
-rw-r--r--src/mem/ruby/system/RubySystem.py1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index ba261cc36..29e395404 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -36,7 +36,6 @@ class RubySystem(ClockedObject):
random_seed = Param.Int(1234, "random seed used by the simulation");
randomization = Param.Bool(False,
"insert random delays on message enqueue times");
- clock = '1GHz'
block_size_bytes = Param.UInt32(64,
"default cache block size; must be a power of two");
mem_size = Param.MemorySize("total memory size of the system");