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| author | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
|---|---|---|
| committer | Nuwan Jayasena <Nuwan.Jayasena@amd.com> | 2012-07-10 22:51:53 -0700 |
| commit | 1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6 (patch) | |
| tree | f804e0cbaae1e2bf7b0037e1b88851c2b64dfd60 /src/mem/ruby/system/SConscript | |
| parent | 4a52a6ea2d84933a1ac8418fe2ba9222832a690d (diff) | |
| download | gem5-1740c4c448a65dee8b27dcdcdccdc1a6e8b4d6b6.tar.xz | |
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Diffstat (limited to 'src/mem/ruby/system/SConscript')
| -rw-r--r-- | src/mem/ruby/system/SConscript | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mem/ruby/system/SConscript b/src/mem/ruby/system/SConscript index cbb1da3b1..baa877b39 100644 --- a/src/mem/ruby/system/SConscript +++ b/src/mem/ruby/system/SConscript @@ -39,6 +39,7 @@ SimObject('DirectoryMemory.py') SimObject('MemoryControl.py') SimObject('WireBuffer.py') SimObject('RubySystem.py') +SimObject('RubyMemoryControl.py') Source('DMASequencer.cc') Source('DirectoryMemory.cc') @@ -46,6 +47,7 @@ Source('SparseMemory.cc') Source('CacheMemory.cc') Source('MemoryControl.cc') Source('WireBuffer.cc') +Source('RubyMemoryControl.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') Source('RubyPort.cc') |