ruby: mesi coherence protocol: invalidate lock

The MESI CMP directory coherence protocol, while transitioning from SM to IM,
did not invalidate the lock that it might have taken on a cache line. This
patch adds an action for doing so.

The problem was found by Dibakar, but I was not happy with his proposed
solution. So I implemented a different solution.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

1 files changed, 14 insertions, 1 deletions

diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index f00f8407a..54fb83dd0 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -306,6 +306,20 @@ Sequencer::removeRequest(SequencerRequest* srequest)
     markRemoved();
 }
 
+void
+Sequencer::invalidateSC(const Address& address)
+{
+    RequestTable::iterator i = m_writeRequestTable.find(address);
+    if (i != m_writeRequestTable.end()) {
+        SequencerRequest* request = i->second;
+        // The controller has lost the coherence permissions, hence the lock
+        // on the cache line maintained by the cache should be cleared.
+        if (request->m_type == RubyRequestType_Store_Conditional) {
+            m_dataCache_ptr->clearLocked(address);
+        }
+    }
+}
+
 bool
 Sequencer::handleLlsc(const Address& address, SequencerRequest* request)
 {
@@ -392,7 +406,6 @@ Sequencer::writeCallback(const Address& address,
            (request->m_type == RubyRequestType_Locked_RMW_Write) ||
            (request->m_type == RubyRequestType_FLUSH));
 
-
     //
     // For Alpha, properly handle LL, SC, and write requests with respect to
     // locked cache blocks.