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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-18 13:27:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-18 13:27:47 -0500 |
| commit | 96c999fe88a5f600a1a5ddf8c15eadba3051508b (patch) | |
| tree | b1fb5220ffcd3b0688d53cb7f41a6c016eadc0fa /src/mem/ruby/system/Sequencer.cc | |
| parent | 216529bf182f58830cfccad090f348e1b8730675 (diff) | |
| download | gem5-96c999fe88a5f600a1a5ddf8c15eadba3051508b.tar.xz | |
ruby: print addresses in hex
Changeset 4872dbdea907 replaced Address by Addr, but did not make changes to
print statements. So the addresses which were being printed in hex earlier
along with their line address, were now being printed in decimals. This patch
adds a function printAddress(Addr) that can be used to print the address in hex
along with the lines address. This function has been put to use in some of the
places. At other places, change has been made to print just the address in
hex.
Diffstat (limited to 'src/mem/ruby/system/Sequencer.cc')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index 815e270b6..aa4ac742a 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -443,7 +443,7 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %d cycles\n", curTick(), m_version, "Seq", llscSuccess ? "Done" : "SC_Failed", "", "", - request_address, total_latency); + printAddress(request_address), total_latency); // update the data unless it is a non-data-carrying flush if (RubySystem::getWarmupEnabled()) { @@ -610,7 +610,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) DPRINTFR(ProtocolTrace, "%15s %3s %10s%20s %6s>%-6s %#x %s\n", curTick(), m_version, "Seq", "Begin", "", "", - msg->getPhysicalAddress(), + printAddress(msg->getPhysicalAddress()), RubyRequestType_to_string(secondary_type)); // The Sequencer currently assesses instruction and data cache hit latency |