ruby: Working M5 interface and updated Ruby interface.

This changeset also includes a lot of work from Derek Hower <drh5@cs.wisc.edu>

RubyMemory is now both a driver for Ruby and a port for M5.  Changed
makeRequest/hitCallback interface. Brought packets (superficially)
into the sequencer. Modified tester infrastructure to be packet based.
and Ruby can be used together through the example ruby_se.py
script. SPARC parallel applications work, and the timing *seems* right
from combined M5/Ruby debug traces. To run,
% build/ALPHA_SE/m5.debug configs/example/ruby_se.py -c
  tests/test-progs/hello/bin/alpha/linux/hello -n 4 -t

1 files changed, 5 insertions, 3 deletions

diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index f4cc03131..d34a2fd3e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -45,13 +45,13 @@
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/gems_common/Map.hh"
-#include "mem/packet.hh"
 
 class DataBlock;
 class AbstractChip;
 class CacheMsg;
 class Address;
 class MachineID;
+class Packet;
 
 class Sequencer : public Consumer {
 public:
@@ -103,8 +103,7 @@ public:
   void printDebug();
 
   // called by Tester or Simics
-  void makeRequest(const Packet* pkt, void* data);
-  void makeRequest(const CacheMsg& request); // depricate this function
+  void makeRequest(Packet* pkt);
   bool doRequest(const CacheMsg& request);
   void issueRequest(const CacheMsg& request);
   bool isReady(const Packet* pkt) const;
@@ -143,6 +142,9 @@ private:
   // One request table per SMT thread
   Map<Address, CacheMsg>** m_writeRequestTable_ptr;
   Map<Address, CacheMsg>** m_readRequestTable_ptr;
+
+  Map<Address, Packet*>* m_packetTable_ptr;
+
   // Global outstanding request count, across all request tables
   int m_outstanding_count;
   bool m_deadlock_check_scheduled;