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| author | Derek Hower <drh5@cs.wisc.edu> | 2009-05-11 10:38:45 -0700 |
|---|---|---|
| committer | Derek Hower <drh5@cs.wisc.edu> | 2009-05-11 10:38:45 -0700 |
| commit | 3d2acc547c53d93dd8ab342e29d5bf4d0bad7719 (patch) | |
| tree | 82e5953eea152b6a2aada4eaa68b13e0d1f475fa /src/mem/ruby/system/Sequencer.hh | |
| parent | e1915f16d140f568dc713820189455cfdf5f9772 (diff) | |
| download | gem5-3d2acc547c53d93dd8ab342e29d5bf4d0bad7719.tar.xz | |
ruby: added Packet interface to makeRequest and isReady.
Also pushed Packet usage into the Sequencer
Diffstat (limited to 'src/mem/ruby/system/Sequencer.hh')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.hh | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh index 5dd674655..cd936a528 100644 --- a/src/mem/ruby/system/Sequencer.hh +++ b/src/mem/ruby/system/Sequencer.hh @@ -45,6 +45,7 @@ #include "GenericMachineType.hh" #include "PrefetchBit.hh" #include "Map.hh" +#include "packet.hh" class DataBlock; class AbstractChip; @@ -108,10 +109,12 @@ public: void printDebug(); // called by Tester or Simics - void makeRequest(const CacheMsg& request); + void makeRequest(const Packet* pkt, void* data); + void makeRequest(const CacheMsg& request); // depricate this function bool doRequest(const CacheMsg& request); void issueRequest(const CacheMsg& request); - bool isReady(const CacheMsg& request) const; + bool isReady(const Packet* pkt) const; + bool isReady(const CacheMsg& request) const; // depricate this function bool empty() const; void resetRequestTime(const Address& addr, int thread); Address getLogicalAddressOfRequest(Address address, int thread); |