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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-23 19:16:16 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-02-23 19:16:16 -0600 |
| commit | 7e27860ef4e5016f5a3c907fbe4c7858f83c8100 (patch) | |
| tree | 24dddb6be57a6e5e959e91fc79eeac6a5c576703 /src/mem/ruby/system/Sequencer.py | |
| parent | 5755fff99811a334874026c465ccebb9b0627230 (diff) | |
| download | gem5-7e27860ef4e5016f5a3c907fbe4c7858f83c8100.tar.xz | |
ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly. Therefore the packets between the io devices and the interrupt
controller do not go through ruby. This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination. Note that the patch does not make these packets go through the
ruby network. That would happen in a subsequent patch.
Diffstat (limited to 'src/mem/ruby/system/Sequencer.py')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 68d02f53c..8ebd63dee 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -35,12 +35,16 @@ class RubyPort(MemObject): type = 'RubyPort' abstract = True cxx_header = "mem/ruby/system/RubyPort.hh" + version = Param.Int(0, "") + slave = VectorSlavePort("CPU slave port") master = VectorMasterPort("CPU master port") - version = Param.Int(0, "") - pio_port = MasterPort("Ruby_pio_port") + pio_master_port = MasterPort("Ruby mem master port") + mem_master_port = MasterPort("Ruby mem master port") + pio_slave_port = SlavePort("Ruby pio slave port") + mem_slave_port = SlavePort("Ruby memory port") + using_ruby_tester = Param.Bool(False, "") - using_network_tester = Param.Bool(False, "") access_phys_mem = Param.Bool(False, "should the rubyport atomically update phys_mem") ruby_system = Param.RubySystem("") @@ -58,12 +62,14 @@ class RubySequencer(RubyPort): type = 'RubySequencer' cxx_class = 'Sequencer' cxx_header = "mem/ruby/system/Sequencer.hh" + icache = Param.RubyCache("") dcache = Param.RubyCache("") max_outstanding_requests = Param.Int(16, "max requests (incl. prefetches) outstanding") deadlock_threshold = Param.Cycles(500000, "max outstanding cycles for a request before deadlock/livelock declared") + using_network_tester = Param.Bool(False, "") class DMASequencer(RubyPort): type = 'DMASequencer' |