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authorJoel Hestness <jthestness@gmail.com>2015-08-14 00:19:37 -0500
committerJoel Hestness <jthestness@gmail.com>2015-08-14 00:19:37 -0500
commit9567c839fecfdb29a59f9da50cf706fcb22a2bb1 (patch)
tree395d523bf8b5ffa038f2be1c9f60923b91d26bfa /src/mem/ruby/system/Sequencer.py
parentc58bee829f88e7360b631771852efa097388a5da (diff)
downloadgem5-9567c839fecfdb29a59f9da50cf706fcb22a2bb1.tar.xz
ruby: Remove the RubyCache/CacheMemory latency
The RubyCache (CacheMemory) latency parameter is only used for top-level caches instantiated for Ruby coherence protocols. However, the top-level cache hit latency is assessed by the Sequencer as accesses flow through to the cache hierarchy. Further, protocol state machines should be enforcing these cache hit latencies, but RubyCaches do not expose their latency to any existng state machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter is superfluous for all caches. This is confusing for users. As a step toward pushing L0/L1 cache hit latency into the top-level cache controllers, move their latencies out of the RubyCache declarations and over to their Sequencers. Eventually, these Sequencer parameters should be exposed as parameters to the top-level cache controllers, which should assess the latency. NOTE: Assessing these latencies in the cache controllers will require modifying each to eliminate instantaneous Ruby hit callbacks in transitions that finish accesses, which is likely a large undertaking.
Diffstat (limited to 'src/mem/ruby/system/Sequencer.py')
-rw-r--r--src/mem/ruby/system/Sequencer.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index e545000cf..7494986e9 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -61,6 +61,12 @@ class RubySequencer(RubyPort):
icache = Param.RubyCache("")
dcache = Param.RubyCache("")
+ # Cache latencies currently assessed at the beginning of each access
+ # NOTE: Setting these values to a value greater than one will result in
+ # O3 CPU pipeline bubbles and negatively impact performance
+ # TODO: Latencies should be migrated into each top-level cache controller
+ icache_hit_latency = Param.Cycles(1, "Inst cache hit latency")
+ dcache_hit_latency = Param.Cycles(1, "Data cache hit latency")
max_outstanding_requests = Param.Int(16,
"max requests (incl. prefetches) outstanding")
deadlock_threshold = Param.Cycles(500000,