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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-11-06 05:41:44 -0600 |
| commit | 95a0b184314cf0171a20fb7e71c845891dc56496 (patch) | |
| tree | 00590e68aa9d66c225a8f0d08f82eca2771e461d /src/mem/ruby/system/Sequencer.py | |
| parent | 8ccfd9defa930d5c2904134d7a7286682e721db9 (diff) | |
| download | gem5-95a0b184314cf0171a20fb7e71c845891dc56496.tar.xz | |
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.
Diffstat (limited to 'src/mem/ruby/system/Sequencer.py')
| -rw-r--r-- | src/mem/ruby/system/Sequencer.py | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index 8bad83db5..6f64207dc 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -73,12 +73,9 @@ class RubySequencer(RubyPort): class DMASequencer(MemObject): type = 'DMASequencer' cxx_header = "mem/ruby/system/DMASequencer.hh" - version = Param.Int(0, "") + version = Param.Int(0, "") slave = SlavePort("Device slave port") - using_ruby_tester = Param.Bool(False, "") - access_phys_mem = Param.Bool(True, - "should the dma atomically update phys_mem") ruby_system = Param.RubySystem(Parent.any, "") system = Param.System(Parent.any, "system object") |