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authorBrad Beckmann <Brad.Beckmann@amd.com>2012-04-06 13:47:07 -0700
committerBrad Beckmann <Brad.Beckmann@amd.com>2012-04-06 13:47:07 -0700
commit5dfa4cd3f5f0091ea8edf1e3673743b48836650d (patch)
tree19ea71dcc665ef9731cc107afc2a42c311be228f /src/mem/ruby/system/System.hh
parent70682e36ddebee06a8658d7fee05ccea519d276c (diff)
downloadgem5-5dfa4cd3f5f0091ea8edf1e3673743b48836650d.tar.xz
sim-ruby: checkpointing fixes and dependent eventq improvements
Fixes checkpointing with respect to lost events after swapping event queues. Also adds DPRINTFs to better understand what's going on when Ruby serializes and unserializes.
Diffstat (limited to 'src/mem/ruby/system/System.hh')
-rw-r--r--src/mem/ruby/system/System.hh7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index 461abffe2..d7d01bcac 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -129,6 +129,13 @@ class RubySystem : public SimObject
void registerAbstractController(AbstractController*);
void registerSparseMemory(SparseMemory*);
+ bool eventQueueEmpty() { return eventq->empty(); }
+ void enqueueRubyEvent(Tick tick)
+ {
+ RubyEvent* e = new RubyEvent(this);
+ schedule(e, tick);
+ }
+
private:
// Private copy constructor and assignment operator
RubySystem(const RubySystem& obj);