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| author | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 18:20:12 -0700 |
|---|---|---|
| committer | Lisa Hsu <Lisa.Hsu@amd.com> | 2011-03-31 18:20:12 -0700 |
| commit | 01fc529bb2e2bf2021b5ec0c0e88136f1665abe6 (patch) | |
| tree | 7c5a9fd1985b7ba88208de22012d70a2130f6673 /src/mem/ruby/system/WireBuffer.py | |
| parent | d857105b5a56bf08f00f17f62a023d8ee3bbcc14 (diff) | |
| download | gem5-01fc529bb2e2bf2021b5ec0c0e88136f1665abe6.tar.xz | |
CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return
a return value. In protocols where you just want to allocate a block
but do not want that block to be your implicitly passed cache_entry, use this function.
Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(),
and if you do a dummy assignment Entry foo := cache.allocate(address), the C++
compiler will complain of an unused variable. This is kind of a hack to get around
those issues, but suggestions welcome.
Diffstat (limited to 'src/mem/ruby/system/WireBuffer.py')
| -rw-r--r-- | src/mem/ruby/system/WireBuffer.py | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py index 0bcc291bb..bca19b4df 100644 --- a/src/mem/ruby/system/WireBuffer.py +++ b/src/mem/ruby/system/WireBuffer.py @@ -28,7 +28,6 @@ from m5.params import * from m5.SimObject import SimObject -#from Controller import RubyController class RubyWireBuffer(SimObject): type = 'RubyWireBuffer' |