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authorPolina Dudnik <pdudnik@gmail.com>2009-08-14 14:06:14 -0500
committerPolina Dudnik <pdudnik@gmail.com>2009-08-14 14:06:14 -0500
commit4b924fd16cf64f242aa4832c13f38fd96c7c1fa0 (patch)
tree7a9d888449044a5f60178a924054819ba7a755ec /src/mem/ruby/system
parent35082a67b65457e36cffdc5f8a13aacaa4258939 (diff)
downloadgem5-4b924fd16cf64f242aa4832c13f38fd96c7c1fa0.tar.xz
SMT atomics modifications:
don't allow enquing from other threads if servicing and atomic for a thread
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r--src/mem/ruby/system/Sequencer.cc31
-rw-r--r--src/mem/ruby/system/Sequencer.hh5
2 files changed, 32 insertions, 4 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index a030fc7c2..cd079cdc3 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -61,6 +61,8 @@ void Sequencer::init(const vector<string> & argv)
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
m_controller = NULL;
+ m_servicing_atomic = -1;
+ m_atomics_counter = 0;
for (size_t i=0; i<argv.size(); i+=2) {
if ( argv[i] == "controller") {
m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache"
@@ -342,7 +344,7 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
}
// Returns true if the sequencer already has a load or store outstanding
-bool Sequencer::isReady(const RubyRequest& request) const {
+bool Sequencer::isReady(const RubyRequest& request) {
// POLINA: check if we are currently flushing the write buffer, if so Ruby is returned as not ready
// to simulate stalling of the front-end
// Do we stall all the sequencers? If it is atomic instruction - yes!
@@ -357,6 +359,31 @@ bool Sequencer::isReady(const RubyRequest& request) const {
return false;
}
+ if (m_servicing_atomic != -1 && m_servicing_atomic != (int)request.proc_id) {
+ assert(m_atomics_counter > 0);
+ return false;
+ }
+ else {
+ if (request.type == RubyRequestType_RMW_Read) {
+ if (m_servicing_atomic == -1) {
+ assert(m_atomics_counter == 0);
+ m_servicing_atomic = (int)request.proc_id;
+ }
+ else {
+ assert(m_servicing_atomic == (int)request.proc_id);
+ }
+ m_atomics_counter++;
+ }
+ else if (request.type == RubyRequestType_RMW_Write) {
+ assert(m_servicing_atomic == (int)request.proc_id);
+ assert(m_atomics_counter > 0);
+ m_atomics_counter--;
+ if (m_atomics_counter == 0) {
+ m_servicing_atomic = -1;
+ }
+ }
+ }
+
return true;
}
@@ -438,7 +465,7 @@ void Sequencer::issueRequest(const RubyRequest& request) {
}
Address line_addr(request.paddr);
line_addr.makeLineAddress();
- CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc), amtype, request.len, PrefetchBit_No);
+ CacheMsg msg(line_addr, Address(request.paddr), ctype, Address(request.pc), amtype, request.len, PrefetchBit_No, request.proc_id);
if (Debug::getProtocolTrace()) {
g_system_ptr->getProfiler()->profileTransition("Seq", m_version, Address(request.paddr),
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 9b55e9781..2b1f023c5 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -84,7 +84,7 @@ public:
// called by Tester or Simics
int64_t makeRequest(const RubyRequest & request);
- bool isReady(const RubyRequest& request) const;
+ bool isReady(const RubyRequest& request);
bool empty() const;
void print(ostream& out) const;
@@ -125,7 +125,8 @@ private:
// Global outstanding request count, across all request tables
int m_outstanding_count;
bool m_deadlock_check_scheduled;
-
+ int m_servicing_atomic;
+ int m_atomics_counter;
};
// Output operator declaration