merge

4 files changed, 89 insertions, 6 deletions

diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 941073ad2..625d5ce59 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -116,6 +116,9 @@ public:
   void setMemoryValue(const Address& addr, char* value,
                       unsigned int size_in_bytes );
 
+  void setLocked (const Address& addr, int context);
+  void clearLocked (const Address& addr);
+  bool isLocked (const Address& addr, int context);
   // Print cache contents
   void print(ostream& out) const;
   void printData(ostream& out) const;
@@ -147,6 +150,7 @@ private:
   // The first index is the # of cache lines.
   // The second index is the the amount associativity.
   Vector<Vector<AbstractCacheEntry*> > m_cache;
+  Vector<Vector<int> > m_locked;
 
   AbstractReplacementPolicy *m_replacementPolicy_ptr;
 
@@ -252,10 +256,13 @@ void CacheMemory::init(const vector<string> & argv)
     assert(false);
 
   m_cache.setSize(m_cache_num_sets);
+  m_locked.setSize(m_cache_num_sets);
   for (int i = 0; i < m_cache_num_sets; i++) {
     m_cache[i].setSize(m_cache_assoc);
+    m_locked[i].setSize(m_cache_assoc);
     for (int j = 0; j < m_cache_assoc; j++) {
       m_cache[i][j] = NULL;
+      m_locked[i][j] = -1;
     }
   }
 }
@@ -474,6 +481,7 @@ void CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
       m_cache[cacheSet][i] = entry;  // Init entry
       m_cache[cacheSet][i]->m_Address = address;
       m_cache[cacheSet][i]->m_Permission = AccessPermission_Invalid;
+      m_locked[cacheSet][i] = -1;
 
       m_replacementPolicy_ptr->touch(cacheSet, i, g_eventQueue_ptr->getTime());
 
@@ -494,6 +502,7 @@ void CacheMemory::deallocate(const Address& address)
   if (location != -1){
     delete m_cache[cacheSet][location];
     m_cache[cacheSet][location] = NULL;
+    m_locked[cacheSet][location] = -1;
   }
 }
 
@@ -542,6 +551,9 @@ void CacheMemory::changePermission(const Address& address, AccessPermission new_
 {
   assert(address == line_address(address));
   lookup(address).m_Permission = new_perm;
+  Index cacheSet = addressToCacheSet(address);
+  int loc = findTagInSet(cacheSet, address);
+  m_locked[cacheSet][loc] = -1; 
   assert(getPermission(address) == new_perm);
 }
 
@@ -630,5 +642,38 @@ void CacheMemory::setMemoryValue(const Address& addr, char* value,
   //  entry = lookup(line_address(addr));
 }
 
+inline
+void 
+CacheMemory::setLocked(const Address& address, int context) 
+{  
+  assert(address == line_address(address));
+  Index cacheSet = addressToCacheSet(address);
+  int loc = findTagInSet(cacheSet, address);
+  assert(loc != -1);
+  m_locked[cacheSet][loc] = context;
+}
+
+inline
+void 
+CacheMemory::clearLocked(const Address& address) 
+{
+  assert(address == line_address(address));
+  Index cacheSet = addressToCacheSet(address);
+  int loc = findTagInSet(cacheSet, address);
+  assert(loc != -1);
+  m_locked[cacheSet][loc] = -1;
+}
+
+inline
+bool
+CacheMemory::isLocked(const Address& address, int context)
+{
+  assert(address == line_address(address));
+  Index cacheSet = addressToCacheSet(address);
+  int loc = findTagInSet(cacheSet, address);
+  assert(loc != -1);
+  return m_locked[cacheSet][loc] == context; 
+}
+
 #endif //CACHEMEMORY_H
 
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 5da7ea51e..58ec7bb45 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -47,7 +47,10 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request)
     break;
   case RubyRequestType_NULL:
   case RubyRequestType_IFETCH:
-  case RubyRequestType_RMW:
+  case RubyRequestType_Locked_Read:
+  case RubyRequestType_Locked_Write:
+  case RubyRequestType_RMW_Read:
+  case RubyRequestType_RMW_Write:
     assert(0);
   }
 
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 97416d2d3..1587aa5fa 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -43,6 +43,8 @@
 
 //Sequencer::Sequencer(int core_id, MessageBuffer* mandatory_q)
 
+#define LLSC_FAIL -2
+
 Sequencer::Sequencer(const string & name)
   :RubyPort(name)
 {
@@ -201,7 +203,10 @@ bool Sequencer::insertRequest(SequencerRequest* request) {
   Address line_addr(request->ruby_request.paddr);
   line_addr.makeLineAddress();
   if ((request->ruby_request.type == RubyRequestType_ST) ||
-      (request->ruby_request.type == RubyRequestType_RMW)) {
+      (request->ruby_request.type == RubyRequestType_RMW_Read) ||  
+      (request->ruby_request.type == RubyRequestType_RMW_Write) ||  
+      (request->ruby_request.type == RubyRequestType_Locked_Read) ||  
+      (request->ruby_request.type == RubyRequestType_Locked_Write)) {
     if (m_writeRequestTable.exist(line_addr)) {
       m_writeRequestTable.lookup(line_addr) = request;
       //      return true;
@@ -237,7 +242,10 @@ void Sequencer::removeRequest(SequencerRequest* srequest) {
   Address line_addr(ruby_request.paddr);
   line_addr.makeLineAddress();
   if ((ruby_request.type == RubyRequestType_ST) ||
-      (ruby_request.type == RubyRequestType_RMW)) {
+      (ruby_request.type == RubyRequestType_RMW_Read) ||  
+      (ruby_request.type == RubyRequestType_RMW_Write) ||  
+      (ruby_request.type == RubyRequestType_Locked_Read) ||
+      (ruby_request.type == RubyRequestType_Locked_Write)) {
     m_writeRequestTable.deallocate(line_addr);
   } else {
     m_readRequestTable.deallocate(line_addr);
@@ -256,7 +264,14 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data) {
   removeRequest(request);
 
   assert((request->ruby_request.type == RubyRequestType_ST) ||
-         (request->ruby_request.type == RubyRequestType_RMW));
+         (request->ruby_request.type == RubyRequestType_RMW_Read) ||  
+         (request->ruby_request.type == RubyRequestType_RMW_Write) ||  
+         (request->ruby_request.type == RubyRequestType_Locked_Read) ||
+         (request->ruby_request.type == RubyRequestType_Locked_Write));
+  // POLINA: the assumption is that atomics are only on data cache and not instruction cache
+  if (request->ruby_request.type == RubyRequestType_Locked_Read) {
+    m_dataCache_ptr->setLocked(address, m_version);
+  }
 
   hitCallback(request, data);
 }
@@ -347,6 +362,7 @@ bool Sequencer::empty() const {
   return (m_writeRequestTable.size() == 0) && (m_readRequestTable.size() == 0);
 }
 
+
 int64_t Sequencer::makeRequest(const RubyRequest & request)
 {
   assert(Address(request.paddr).getOffset() + request.len <= RubySystem::getBlockSizeBytes());
@@ -355,6 +371,16 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
     SequencerRequest *srequest = new SequencerRequest(request, id, g_eventQueue_ptr->getTime());
     bool found = insertRequest(srequest);
     if (!found)
+      if (request.type == RubyRequestType_Locked_Write) {
+        // NOTE: it is OK to check the locked flag here as the mandatory queue will be checked first
+        // ensuring that nothing comes between checking the flag and servicing the store
+        if (!m_dataCache_ptr->isLocked(line_address(Address(request.paddr)), m_version)) {
+          return LLSC_FAIL;
+        }
+        else {
+          m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
+        }
+      }
       issueRequest(request);
 
     // TODO: issue hardware prefetches here
@@ -379,7 +405,16 @@ void Sequencer::issueRequest(const RubyRequest& request) {
   case RubyRequestType_ST:
     ctype = CacheRequestType_ST;
     break;
-  case RubyRequestType_RMW:
+  case RubyRequestType_Locked_Read:
+    ctype = CacheRequestType_ST;
+    break;
+  case RubyRequestType_Locked_Write:
+    ctype = CacheRequestType_ST;
+    break;
+  case RubyRequestType_RMW_Read:
+    ctype = CacheRequestType_ATOMIC;
+    break;
+  case RubyRequestType_RMW_Write:
     ctype = CacheRequestType_ATOMIC;
     break;
   default:
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index 40c425ad7..8cbeb2b0e 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -106,7 +106,7 @@ public:
   static int getNumberOfSequencers() { return m_sequencers.size(); }
 
   Profiler* getProfiler() {assert(m_profiler_ptr != NULL); return m_profiler_ptr; }
-  Tracer* getTracer() { assert(m_tracer_ptr != NULL); return m_tracer_ptr; }
+  static Tracer* getTracer() { assert(m_tracer_ptr != NULL); return m_tracer_ptr; }
   static MemoryVector* getMemoryVector() { assert(m_mem_vec_ptr != NULL); return m_mem_vec_ptr;}
 
   void recordCacheContents(CacheRecorder& tr) const;