diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:34 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-01-29 20:29:34 -0800 |
commit | 143d8ea698a832d80afb1a0cd6726cee1d47d4b5 (patch) | |
tree | abfade3899e0dfde27e220a381dd8636a2785992 /src/mem/ruby/system | |
parent | 90aab239a150f8c998b16ff0a6c297ec0ef065c2 (diff) | |
download | gem5-143d8ea698a832d80afb1a0cd6726cee1d47d4b5.tar.xz |
ruby: removed last level cache support
Removed the last level cache support and MOESI_hammer's dependency on it.
Replaces the LLC support with the more generic MachineType count.
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r-- | src/mem/ruby/system/CacheMemory.cc | 23 | ||||
-rw-r--r-- | src/mem/ruby/system/CacheMemory.hh | 8 |
2 files changed, 0 insertions, 31 deletions
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc index 8c5112183..110dce2d0 100644 --- a/src/mem/ruby/system/CacheMemory.cc +++ b/src/mem/ruby/system/CacheMemory.cc @@ -28,9 +28,6 @@ #include "mem/ruby/system/CacheMemory.hh" -int CacheMemory::m_num_last_level_caches = 0; -MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST; - // ******************* Definitions ******************* // Output operator definition @@ -75,19 +72,6 @@ void CacheMemory::init() else assert(false); - m_num_last_level_caches = - MachineType_base_count(MachineType_FIRST); -#if 0 - for (uint32 i=0; i<argv.size(); i+=2) { - if (m_last_level_machine_type < m_controller->getMachineType()) { - m_num_last_level_caches = - MachineType_base_count(m_controller->getMachineType()); - m_last_level_machine_type = - m_controller->getMachineType(); - } - } -#endif - m_cache.setSize(m_cache_num_sets); m_locked.setSize(m_cache_num_sets); for (int i = 0; i < m_cache_num_sets; i++) { @@ -112,13 +96,6 @@ CacheMemory::~CacheMemory() } } -int -CacheMemory::numberOfLastLevelCaches() -{ - return m_num_last_level_caches; -} - - void CacheMemory::printConfig(ostream& out) { out << "Cache config: " << m_cache_name << endl; diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh index f70427f2d..74eb5d68d 100644 --- a/src/mem/ruby/system/CacheMemory.hh +++ b/src/mem/ruby/system/CacheMemory.hh @@ -106,8 +106,6 @@ public: AccessPermission getPermission(const Address& address) const; void changePermission(const Address& address, AccessPermission new_perm); - static int numberOfLastLevelCaches(); - int getLatency() const { return m_latency; } // Hook for checkpointing the contents of the cache @@ -172,12 +170,6 @@ private: int m_cache_num_sets; int m_cache_num_set_bits; int m_cache_assoc; - - static Vector< CacheMemory* > m_all_caches; - - static int m_num_last_level_caches; - static MachineType m_last_level_machine_type; - }; #endif //CACHEMEMORY_H |