sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.

7 files changed, 10 insertions, 0 deletions

diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index 57326c3c6..4b0269822 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -34,6 +34,7 @@ from Controller import RubyController
 class RubyCache(SimObject):
     type = 'RubyCache'
     cxx_class = 'CacheMemory'
+    cxx_header = "mem/ruby/system/CacheMemory.hh"
     size = Param.MemorySize("capacity in bytes");
     latency = Param.Int("");
     assoc = Param.Int("");
diff --git a/src/mem/ruby/system/DirectoryMemory.py b/src/mem/ruby/system/DirectoryMemory.py
index d3b6bc591..ac4dd5934 100644
--- a/src/mem/ruby/system/DirectoryMemory.py
+++ b/src/mem/ruby/system/DirectoryMemory.py
@@ -34,6 +34,7 @@ from m5.SimObject import SimObject
 class RubyDirectoryMemory(SimObject):
     type = 'RubyDirectoryMemory'
     cxx_class = 'DirectoryMemory'
+    cxx_header = "mem/ruby/system/DirectoryMemory.hh"
     version = Param.Int(0, "")
     size = Param.MemorySize("1GB", "capacity in bytes")
     use_map = Param.Bool(False, "enable sparse memory")
diff --git a/src/mem/ruby/system/MemoryControl.py b/src/mem/ruby/system/MemoryControl.py
index 09c940fee..ad18efec5 100644
--- a/src/mem/ruby/system/MemoryControl.py
+++ b/src/mem/ruby/system/MemoryControl.py
@@ -34,5 +34,6 @@ class MemoryControl(ClockedObject):
     abstract = True
     type = 'MemoryControl'
     cxx_class = 'MemoryControl'
+    cxx_header = "mem/ruby/system/MemoryControl.hh"
     version = Param.Int("");
     ruby_system = Param.RubySystem("")
diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py
index e65b6f5cc..7764938d3 100644
--- a/src/mem/ruby/system/RubyMemoryControl.py
+++ b/src/mem/ruby/system/RubyMemoryControl.py
@@ -34,6 +34,7 @@ from MemoryControl import MemoryControl
 class RubyMemoryControl(MemoryControl):
     type = 'RubyMemoryControl'
     cxx_class = 'RubyMemoryControl'
+    cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
     version = Param.Int("");
 
     # Override the default clock
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index c9d2e96ac..b1f625723 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -32,6 +32,7 @@ from ClockedObject import ClockedObject
 
 class RubySystem(ClockedObject):
     type = 'RubySystem'
+    cxx_header = "mem/ruby/system/System.hh"
     random_seed = Param.Int(1234, "random seed used by the simulation");
     randomization = Param.Bool(False,
         "insert random delays on message enqueue times");
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index deef6e714..9b243a8b9 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -34,6 +34,7 @@ from MemObject import MemObject
 class RubyPort(MemObject):
     type = 'RubyPort'
     abstract = True
+    cxx_header = "mem/ruby/system/RubyPort.hh"
     slave = VectorSlavePort("CPU slave port")
     master = VectorMasterPort("CPU master port")
     version = Param.Int(0, "")
@@ -50,10 +51,12 @@ class RubyPort(MemObject):
 
 class RubyPortProxy(RubyPort):
     type = 'RubyPortProxy'
+    cxx_header = "mem/ruby/system/RubyPortProxy.hh"
     
 class RubySequencer(RubyPort):
     type = 'RubySequencer'
     cxx_class = 'Sequencer'
+    cxx_header = "mem/ruby/system/Sequencer.hh"
     icache = Param.RubyCache("")
     dcache = Param.RubyCache("")
     max_outstanding_requests = Param.Int(16,
@@ -63,3 +66,4 @@ class RubySequencer(RubyPort):
 
 class DMASequencer(RubyPort):
     type = 'DMASequencer'
+    cxx_header = "mem/ruby/system/DMASequencer.hh"
diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py
index bca19b4df..f48ab1f95 100644
--- a/src/mem/ruby/system/WireBuffer.py
+++ b/src/mem/ruby/system/WireBuffer.py
@@ -32,3 +32,4 @@ from m5.SimObject import SimObject
 class RubyWireBuffer(SimObject):
     type = 'RubyWireBuffer'
     cxx_class = 'WireBuffer'
+    cxx_header = "mem/ruby/system/WireBuffer.hh"