ruby: get "using namespace" out of headers

In addition to obvious changes, this required a slight change to the slicc
grammar to allow types with :: in them.  Otherwise slicc barfs on std::string
which we need for the headers that slicc generates.

20 files changed, 111 insertions, 87 deletions

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 10ea8a6fc..1e188fb60 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -28,6 +28,8 @@
 
 #include "mem/ruby/system/CacheMemory.hh"
 
+using namespace std;
+
 ostream&
 operator<<(ostream& out, const CacheMemory& obj)
 {
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index bdf2bb25c..21756a606 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -29,6 +29,8 @@
 #ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
 #define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
 
+#include <iostream>
+#include <string>
 #include <vector>
 
 #include "base/hashmap.hh"
@@ -61,7 +63,7 @@ class CacheMemory : public SimObject
     void init();
 
     // Public Methods
-    void printConfig(ostream& out);
+    void printConfig(std::ostream& out);
 
     // perform a cache access and see if we hit or not.  Return true on a hit.
     bool tryCacheAccess(const Address& address, CacheRequestType type,
@@ -120,11 +122,11 @@ class CacheMemory : public SimObject
     void clearLocked (const Address& addr);
     bool isLocked (const Address& addr, int context);
     // Print cache contents
-    void print(ostream& out) const;
-    void printData(ostream& out) const;
+    void print(std::ostream& out) const;
+    void printData(std::ostream& out) const;
 
     void clearStats() const;
-    void printStats(ostream& out) const;
+    void printStats(std::ostream& out) const;
 
   private:
     // convert a Address to its location in the cache
@@ -141,7 +143,7 @@ class CacheMemory : public SimObject
     CacheMemory& operator=(const CacheMemory& obj);
 
   private:
-    const string m_cache_name;
+    const std::string m_cache_name;
     int m_latency;
 
     // Data Members (m_prefix)
@@ -159,7 +161,7 @@ class CacheMemory : public SimObject
     CacheProfiler* m_profiler_ptr;
 
     int m_cache_size;
-    string m_policy;
+    std::string m_policy;
     int m_cache_num_sets;
     int m_cache_num_set_bits;
     int m_cache_assoc;
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 315dab62a..5d9037358 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -164,7 +164,7 @@ DMASequencer::ackCallback()
 }
 
 void
-DMASequencer::printConfig(ostream & out)
+DMASequencer::printConfig(std::ostream & out)
 {
 }
 
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index 7fb9b44a0..b3999fb3f 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -31,6 +31,8 @@
 #include "mem/ruby/system/DirectoryMemory.hh"
 #include "mem/ruby/system/System.hh"
 
+using namespace std;
+
 int DirectoryMemory::m_num_directories = 0;
 int DirectoryMemory::m_num_directories_bits = 0;
 uint64_t DirectoryMemory::m_total_size_bytes = 0;
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 4e7bfc4f6..79b04726a 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -29,6 +29,9 @@
 #ifndef __MEM_RUBY_SYSTEM_DIRECTORYMEMORY_HH__
 #define __MEM_RUBY_SYSTEM_DIRECTORYMEMORY_HH__
 
+#include <iostream>
+#include <string>
+
 #include "mem/protocol/Directory_Entry.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -52,15 +55,15 @@ class DirectoryMemory : public SimObject
     bool isSparseImplementation() { return m_use_map; }
     uint64 getSize() { return m_size_bytes; }
 
-    void printConfig(ostream& out) const;
-    static void printGlobalConfig(ostream & out);
+    void printConfig(std::ostream& out) const;
+    static void printGlobalConfig(std::ostream & out);
     bool isPresent(PhysAddress address);
     Directory_Entry& lookup(PhysAddress address);
 
     void invalidateBlock(PhysAddress address);
 
-    void print(ostream& out) const;
-    void printStats(ostream& out) const;
+    void print(std::ostream& out) const;
+    void printStats(std::ostream& out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -68,7 +71,7 @@ class DirectoryMemory : public SimObject
     DirectoryMemory& operator=(const DirectoryMemory& obj);
 
   private:
-    const string m_name;
+    const std::string m_name;
     Directory_Entry **m_entries;
     // int m_size;  // # of memory module blocks this directory is
                     // responsible for
@@ -88,11 +91,11 @@ class DirectoryMemory : public SimObject
     int m_map_levels;
 };
 
-inline ostream&
-operator<<(ostream& out, const DirectoryMemory& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const DirectoryMemory& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
diff --git a/src/mem/ruby/system/MemoryControl.cc b/src/mem/ruby/system/MemoryControl.cc
index 963cc3947..3644a3e59 100644
--- a/src/mem/ruby/system/MemoryControl.cc
+++ b/src/mem/ruby/system/MemoryControl.cc
@@ -104,8 +104,6 @@
  *
  */
 
-#include <list>
-
 #include "base/cprintf.hh"
 #include "mem/gems_common/Map.hh"
 #include "mem/ruby/common/Address.hh"
@@ -118,6 +116,8 @@
 #include "mem/ruby/system/MemoryControl.hh"
 #include "mem/ruby/system/System.hh"
 
+using namespace std;
+
 class Consumer;
 
 // Value to reset watchdog timer to.
diff --git a/src/mem/ruby/system/MemoryControl.hh b/src/mem/ruby/system/MemoryControl.hh
index d42c1e6e0..73646f623 100644
--- a/src/mem/ruby/system/MemoryControl.hh
+++ b/src/mem/ruby/system/MemoryControl.hh
@@ -29,7 +29,9 @@
 #ifndef __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
 #define __MEM_RUBY_SYSTEM_MEMORY_CONTROL_HH__
 
+#include <iostream>
 #include <list>
+#include <string>
 
 #include "mem/gems_common/Map.hh"
 #include "mem/gems_common/util.hh"
@@ -67,8 +69,8 @@ class MemoryControl :
 
     void setConsumer(Consumer* consumer_ptr);
     Consumer* getConsumer() { return m_consumer_ptr; };
-    void setDescription(const string& name) { m_description = name; };
-    string getDescription() { return m_description; };
+    void setDescription(const std::string& name) { m_description = name; };
+    std::string getDescription() { return m_description; };
 
     // Called from the directory:
     void enqueue(const MsgPtr& message, int latency );
@@ -82,11 +84,11 @@ class MemoryControl :
     //// Called from L3 cache:
     //void writeBack(physical_address_t addr);
 
-    void printConfig(ostream& out);
-    void print(ostream& out) const;
+    void printConfig(std::ostream& out);
+    void print(std::ostream& out) const;
     void setDebug(int debugFlag);
     void clearStats() const;
-    void printStats(ostream& out) const;
+    void printStats(std::ostream& out) const;
 
     //added by SS
     int getBanksPerRank() { return m_banks_per_rank; };
@@ -109,7 +111,7 @@ class MemoryControl :
 
     // data members
     Consumer* m_consumer_ptr;  // Consumer to signal a wakeup()
-    string m_description;
+    std::string m_description;
     int m_msg_counter;
     int m_awakened;
 
@@ -136,9 +138,9 @@ class MemoryControl :
     int m_refresh_period_system;
 
     // queues where memory requests live
-    list<MemoryNode> m_response_queue;
-    list<MemoryNode> m_input_queue;
-    list<MemoryNode>* m_bankQueues;
+    std::list<MemoryNode> m_response_queue;
+    std::list<MemoryNode> m_input_queue;
+    std::list<MemoryNode>* m_bankQueues;
 
     // Each entry indicates number of address-bus cycles until bank
     // is reschedulable:
diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh
index f1fb8b2e9..e1d816923 100644
--- a/src/mem/ruby/system/PerfectCacheMemory.hh
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh
@@ -43,8 +43,8 @@ struct PerfectCacheLineState
 };
 
 template<class ENTRY>
-inline ostream&
-operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const PerfectCacheLineState<ENTRY>& obj)
 {
     return out;
 }
@@ -55,7 +55,7 @@ class PerfectCacheMemory
   public:
     PerfectCacheMemory();
 
-    static void printConfig(ostream& out);
+    static void printConfig(std::ostream& out);
 
     // perform a cache access and see if we hit or not.  Return true
     // on a hit.
@@ -86,7 +86,7 @@ class PerfectCacheMemory
     void changePermission(const Address& address, AccessPermission new_perm);
 
     // Print cache contents
-    void print(ostream& out) const;
+    void print(std::ostream& out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -98,11 +98,11 @@ class PerfectCacheMemory
 };
 
 template<class ENTRY>
-inline ostream&
-operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const PerfectCacheMemory<ENTRY>& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
@@ -114,7 +114,7 @@ PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
 
 template<class ENTRY>
 inline void
-PerfectCacheMemory<ENTRY>::printConfig(ostream& out)
+PerfectCacheMemory<ENTRY>::printConfig(std::ostream& out)
 {
 }
 
@@ -206,7 +206,7 @@ PerfectCacheMemory<ENTRY>::changePermission(const Address& address,
 
 template<class ENTRY>
 inline void
-PerfectCacheMemory<ENTRY>::print(ostream& out) const
+PerfectCacheMemory<ENTRY>::print(std::ostream& out) const
 {
 }
 
diff --git a/src/mem/ruby/system/PersistentTable.cc b/src/mem/ruby/system/PersistentTable.cc
index 979a0d4ab..64730ee29 100644
--- a/src/mem/ruby/system/PersistentTable.cc
+++ b/src/mem/ruby/system/PersistentTable.cc
@@ -29,6 +29,8 @@
 #include "mem/gems_common/util.hh"
 #include "mem/ruby/system/PersistentTable.hh"
 
+using namespace std;
+
 // randomize so that handoffs are not locality-aware
 #if 0
 int persistent_randomize[] = {0, 4, 8, 12, 1, 5, 9, 13, 2, 6,
diff --git a/src/mem/ruby/system/PersistentTable.hh b/src/mem/ruby/system/PersistentTable.hh
index 64203c82c..667d68dcb 100644
--- a/src/mem/ruby/system/PersistentTable.hh
+++ b/src/mem/ruby/system/PersistentTable.hh
@@ -29,6 +29,8 @@
 #ifndef __MEM_RUBY_SYSTEM_PERSISTENTTABLE_HH__
 #define __MEM_RUBY_SYSTEM_PERSISTENTTABLE_HH__
 
+#include <iostream>
+
 #include "mem/gems_common/Map.hh"
 #include "mem/protocol/AccessType.hh"
 #include "mem/ruby/common/Address.hh"
@@ -39,7 +41,7 @@
 class PersistentTableEntry
 {
   public:
-    void print(ostream& out) const {}
+    void print(std::ostream& out) const {}
 
     NetDest m_starving;
     NetDest m_marked;
@@ -67,9 +69,9 @@ class PersistentTable
     int countStarvingForAddress(const Address& addr) const;
     int countReadStarvingForAddress(const Address& addr) const;
 
-    static void printConfig(ostream& out) {}
+    static void printConfig(std::ostream& out) {}
 
-    void print(ostream& out) const;
+    void print(std::ostream& out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -80,19 +82,19 @@ class PersistentTable
     Map<Address, PersistentTableEntry>* m_map_ptr;
 };
 
-inline ostream&
-operator<<(ostream& out, const PersistentTable& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const PersistentTable& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
-inline ostream&
-operator<<(ostream& out, const PersistentTableEntry& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const PersistentTableEntry& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 4038c6007..56701cd5c 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -39,8 +39,6 @@
 #include "mem/tport.hh"
 #include "params/RubyPort.hh"
 
-using namespace std;
-
 class MessageBuffer;
 class AbstractController;
 
@@ -110,7 +108,7 @@ class RubyPort : public MemObject
     void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
 
   protected:
-    const string m_name;
+    const std::string m_name;
     void ruby_hit_callback(PacketPtr pkt);
     void hit(PacketPtr pkt);
 
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index a473ccf44..42bf7ebb5 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -43,6 +43,8 @@
 #include "mem/ruby/system/System.hh"
 #include "params/RubySequencer.hh"
 
+using namespace std;
+
 Sequencer *
 RubySequencerParams::create()
 {
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 69fd3b771..a5b2dd544 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -29,6 +29,8 @@
 #ifndef __MEM_RUBY_SYSTEM_SEQUENCER_HH__
 #define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
 
+#include <iostream>
+
 #include "mem/gems_common/Map.hh"
 #include "mem/protocol/AccessModeType.hh"
 #include "mem/protocol/CacheRequestType.hh"
@@ -68,9 +70,9 @@ class Sequencer : public RubyPort, public Consumer
     // Public Methods
     void wakeup(); // Used only for deadlock detection
 
-    void printConfig(ostream& out) const;
+    void printConfig(std::ostream& out) const;
 
-    void printProgress(ostream& out) const;
+    void printProgress(std::ostream& out) const;
 
     void writeCallback(const Address& address, DataBlock& data);
     void readCallback(const Address& address, DataBlock& data);
@@ -79,8 +81,8 @@ class Sequencer : public RubyPort, public Consumer
     RequestStatus getRequestStatus(const RubyRequest& request);
     bool empty() const;
 
-    void print(ostream& out) const;
-    void printStats(ostream & out) const;
+    void print(std::ostream& out) const;
+    void printStats(std::ostream& out) const;
     void checkCoherence(const Address& address);
 
     void removeRequest(SequencerRequest* request);
@@ -133,11 +135,11 @@ class Sequencer : public RubyPort, public Consumer
     SequencerWakeupEvent deadlockCheckEvent;
 };
 
-inline ostream&
-operator<<(ostream& out, const Sequencer& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const Sequencer& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
diff --git a/src/mem/ruby/system/SparseMemory.cc b/src/mem/ruby/system/SparseMemory.cc
index 70e00f14b..c4f636322 100644
--- a/src/mem/ruby/system/SparseMemory.cc
+++ b/src/mem/ruby/system/SparseMemory.cc
@@ -28,6 +28,8 @@
 
 #include "mem/ruby/system/SparseMemory.hh"
 
+using namespace std;
+
 SparseMemory::SparseMemory(int number_of_bits, int number_of_levels)
 {
     int even_level_bits;
diff --git a/src/mem/ruby/system/SparseMemory.hh b/src/mem/ruby/system/SparseMemory.hh
index 2c207aa3f..0601a8ca5 100644
--- a/src/mem/ruby/system/SparseMemory.hh
+++ b/src/mem/ruby/system/SparseMemory.hh
@@ -29,6 +29,8 @@
 #ifndef __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__
 #define __MEM_RUBY_SYSTEM_SPARSEMEMORY_HH__
 
+#include <iostream>
+
 #include "base/hashmap.hh"
 #include "mem/protocol/Directory_Entry.hh"
 #include "mem/ruby/common/Address.hh"
@@ -55,7 +57,7 @@ class SparseMemory
     SparseMemory(int number_of_bits, int number_of_levels);
     ~SparseMemory();
 
-    void printConfig(ostream& out) { }
+    void printConfig(std::ostream& out) { }
 
     bool exist(const Address& address) const;
     void add(const Address& address);
@@ -64,8 +66,8 @@ class SparseMemory
     Directory_Entry* lookup(const Address& address);
 
     // Print cache contents
-    void print(ostream& out) const;
-    void printStats(ostream& out) const;
+    void print(std::ostream& out) const;
+    void printStats(std::ostream& out) const;
 
   private:
     // Private Methods
@@ -93,11 +95,11 @@ class SparseMemory
     uint64_t* m_removes_per_level;
 };
 
-inline ostream&
-operator<<(ostream& out, const SparseMemEntry& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const SparseMemEntry& obj)
 {
     out << "SparseMemEntry";
-    out << flush;
+    out << std::flush;
     return out;
 }
 
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index ef4b66290..418b31bf0 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -36,6 +36,8 @@
 #include "mem/ruby/system/MemoryVector.hh"
 #include "mem/ruby/system/System.hh"
 
+using namespace std;
+
 int RubySystem::m_random_seed;
 bool RubySystem::m_randomization;
 Tick RubySystem::m_clock;
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index ccec2d61c..f501c5a83 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -113,8 +113,8 @@ class RubySystem : public SimObject
     }
 
     void recordCacheContents(CacheRecorder& tr) const;
-    static void printConfig(ostream& out);
-    static void printStats(ostream& out);
+    static void printConfig(std::ostream& out);
+    static void printStats(std::ostream& out);
     void clearStats() const;
 
     uint64 getInstructionCount(int thread) { return 1; }
@@ -124,7 +124,7 @@ class RubySystem : public SimObject
         return g_eventQueue_ptr->getTime();
     }
 
-    void print(ostream& out) const;
+    void print(std::ostream& out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -133,7 +133,7 @@ class RubySystem : public SimObject
 
     void init();
 
-    static void printSystemConfig(ostream& out);
+    static void printSystemConfig(std::ostream& out);
 
   private:
     // configuration parameters
@@ -153,23 +153,23 @@ class RubySystem : public SimObject
     static MemoryVector* m_mem_vec_ptr;
 };
 
-inline ostream&
-operator<<(ostream& out, const RubySystem& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const RubySystem& obj)
 {
     //obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
 class RubyExitCallback : public Callback
 {
   private:
-    string stats_filename;
+    std::string stats_filename;
 
   public:
     virtual ~RubyExitCallback() {}
 
-    RubyExitCallback(const string& _stats_filename)
+    RubyExitCallback(const std::string& _stats_filename)
     {
         stats_filename = _stats_filename;
     }
diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh
index d21946abd..fa1e6c8dd 100644
--- a/src/mem/ruby/system/TBETable.hh
+++ b/src/mem/ruby/system/TBETable.hh
@@ -29,6 +29,8 @@
 #ifndef __MEM_RUBY_SYSTEM_TBETABLE_HH__
 #define __MEM_RUBY_SYSTEM_TBETABLE_HH__
 
+#include <iostream>
+
 #include "mem/gems_common/Map.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Global.hh"
@@ -45,9 +47,9 @@ class TBETable
     }
 
     void
-    printConfig(ostream& out)
+    printConfig(std::ostream& out)
     {
-        out << "TBEs_per_TBETable: " << m_number_of_TBEs << endl;
+        out << "TBEs_per_TBETable: " << m_number_of_TBEs << std::endl;
     }
 
     bool isPresent(const Address& address) const;
@@ -63,7 +65,7 @@ class TBETable
     const ENTRY& lookup(const Address& address) const;
 
     // Print cache contents
-    void print(ostream& out) const;
+    void print(std::ostream& out) const;
 
   private:
     // Private copy constructor and assignment operator
@@ -78,11 +80,11 @@ class TBETable
 };
 
 template<class ENTRY>
-inline ostream&
-operator<<(ostream& out, const TBETable<ENTRY>& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const TBETable<ENTRY>& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }
 
@@ -133,7 +135,7 @@ TBETable<ENTRY>::lookup(const Address& address) const
 
 template<class ENTRY>
 inline void
-TBETable<ENTRY>::print(ostream& out) const
+TBETable<ENTRY>::print(std::ostream& out) const
 {
 }
 
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index eba04e3e3..c623677f3 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -96,7 +96,7 @@ TimerTable::unset(const Address& address)
 }
 
 void
-TimerTable::print(ostream& out) const
+TimerTable::print(std::ostream& out) const
 {
 }
 
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index 96b4b0b15..4c1d2afa3 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -30,6 +30,8 @@
 #define __MEM_RUBY_SYSTEM_TIMERTABLE_HH__
 
 #include <cassert>
+#include <iostream>
+#include <string>
 
 #include "mem/gems_common/Map.hh"
 #include "mem/ruby/common/Address.hh"
@@ -42,7 +44,7 @@ class TimerTable
   public:
     TimerTable();
 
-    static void printConfig(ostream& out) {}
+    static void printConfig(std::ostream& out) {}
 
     void
     setConsumer(Consumer* consumer_ptr)
@@ -52,7 +54,7 @@ class TimerTable
     }
 
     void
-    setDescription(const string& name)
+    setDescription(const std::string& name)
     {
         m_name = name;
     }
@@ -62,7 +64,7 @@ class TimerTable
     bool isSet(const Address& address) const { return m_map.exist(address); }
     void set(const Address& address, Time relative_latency);
     void unset(const Address& address);
-    void print(ostream& out) const;
+    void print(std::ostream& out) const;
 
   private:
     void updateNext() const;
@@ -77,17 +79,14 @@ class TimerTable
     mutable Time m_next_time; // Only valid if m_next_valid is true
     mutable Address m_next_address;  // Only valid if m_next_valid is true
     Consumer* m_consumer_ptr;  // Consumer to signal a wakeup()
-    string m_name;
+    std::string m_name;
 };
 
-// ******************* Definitions *******************
-
-// Output operator definition
-inline ostream&
-operator<<(ostream& out, const TimerTable& obj)
+inline std::ostream&
+operator<<(std::ostream& out, const TimerTable& obj)
 {
     obj.print(out);
-    out << flush;
+    out << std::flush;
     return out;
 }