slicc: added MOESI_CMP_directory, DMA SequencerMsg, parameterized controllers

This changeset contains a lot of different changes that are too
mingled to separate.  They are:

1.  Added MOESI_CMP_directory

I made the changes necessary to bring back MOESI_CMP_directory,
including adding a DMA controller.  I got rid of MOESI_CMP_directory_m
and made MOESI_CMP_directory use a memory controller. Added a new
configuration for two level protocols in general, and
MOESI_CMP_directory in particular.

2.  DMA Sequencer uses a generic SequencerMsg

I will eventually make the cache Sequencer use this type as well.  It
doesn't contain an offset field, just a physical address and a length.
MI_example has been updated to deal with this.

3. Parameterized Controllers

SLICC controllers can now take custom parameters to use for mapping,
latencies, etc.  Currently, only int parameters are supported.

7 files changed, 35 insertions, 36 deletions

diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index d29dba602..8af892007 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -4,9 +4,8 @@
 #include "mem/ruby/slicc_interface/AbstractController.hh"
 
 /* SLICC generated types */
-#include "mem/protocol/DMARequestMsg.hh"
-#include "mem/protocol/DMARequestType.hh"
-#include "mem/protocol/DMAResponseMsg.hh"
+#include "mem/protocol/SequencerMsg.hh"
+#include "mem/protocol/SequencerRequestType.hh"
 #include "mem/ruby/system/System.hh"
 
 DMASequencer::DMASequencer(const string & name)
@@ -66,20 +65,16 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request)
   active_request.bytes_issued = 0;
   active_request.id = makeUniqueRequestID();
 
-  DMARequestMsg msg;
+  SequencerMsg msg;
   msg.getPhysicalAddress() = Address(paddr);
   msg.getLineAddress() = line_address(msg.getPhysicalAddress());
-  msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ;
-  msg.getOffset() = paddr & m_data_block_mask;
-  msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ?
+  msg.getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
+  int offset = paddr & m_data_block_mask;
+  msg.getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
     len : 
-    RubySystem::getBlockSizeBytes() - msg.getOffset();
-  if (write) {
-    msg.getType() = DMARequestType_WRITE;
-    msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen());
-  } else {
-    msg.getType() = DMARequestType_READ;
-  }
+    RubySystem::getBlockSizeBytes() - offset;
+  if (write)
+    msg.getDataBlk().setData(data, offset, msg.getLen());
   m_mandatory_q_ptr->enqueue(msg);
   active_request.bytes_issued += msg.getLen();
 
@@ -96,14 +91,13 @@ void DMASequencer::issueNext()
     return;
   }
 
-  DMARequestMsg msg;
+  SequencerMsg msg;
   msg.getPhysicalAddress() = Address(active_request.start_paddr + 
 				     active_request.bytes_completed);
   assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
   msg.getLineAddress() = line_address(msg.getPhysicalAddress());
-  msg.getOffset() = 0;
-  msg.getType() = (active_request.write ? DMARequestType_WRITE : 
-		   DMARequestType_READ);
+  msg.getType() = (active_request.write ? SequencerRequestType_ST : 
+		   SequencerRequestType_LD);
   msg.getLen() = (active_request.len - 
 		  active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
 		  active_request.len - active_request.bytes_completed :
@@ -111,9 +105,9 @@ void DMASequencer::issueNext()
   if (active_request.write) {
     msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 
 			     0, msg.getLen());
-    msg.getType() = DMARequestType_WRITE;
+    msg.getType() = SequencerRequestType_ST;
   } else {
-    msg.getType() = DMARequestType_READ;
+    msg.getType() = SequencerRequestType_LD;
   }
   m_mandatory_q_ptr->enqueue(msg);
   active_request.bytes_issued += msg.getLen();
diff --git a/src/mem/ruby/system/DirectoryMemory.cc b/src/mem/ruby/system/DirectoryMemory.cc
index b279d21af..c87be94a2 100644
--- a/src/mem/ruby/system/DirectoryMemory.cc
+++ b/src/mem/ruby/system/DirectoryMemory.cc
@@ -58,12 +58,14 @@ void DirectoryMemory::init(const vector<string> & argv)
     if ( (*it) == "version" )
       m_version = atoi( (*(++it)).c_str() );
     else if ( (*it) == "size_mb" ) {
-      m_size_bytes = atoi((*(++it)).c_str()) * (1<<20);
+      m_size_bytes = atoi((*(++it)).c_str()) * static_cast<uint64>(1<<20);
       m_size_bits = log_int(m_size_bytes);
     } else if ( (*it) == "controller" ) {
       m_controller = RubySystem::getController((*(++it)));
-    } else
+    } else {
+      cerr << "DirectoryMemory: Unkown config parameter: " << (*it) << endl;
       assert(0);
+    }
   }
   assert(m_controller != NULL);
 
diff --git a/src/mem/ruby/system/DirectoryMemory.hh b/src/mem/ruby/system/DirectoryMemory.hh
index 6445ecc62..39de679ed 100644
--- a/src/mem/ruby/system/DirectoryMemory.hh
+++ b/src/mem/ruby/system/DirectoryMemory.hh
@@ -59,7 +59,7 @@ public:
   int mapAddressToLocalIdx(PhysAddress address);
   static int mapAddressToDirectoryVersion(PhysAddress address);
 
-  int getSize() { return m_size_bytes; }
+  uint64 getSize() { return m_size_bytes; }
 
   // Public Methods
   void printConfig(ostream& out) const;
@@ -84,8 +84,8 @@ private:
   // Data Members (m_ prefix)
   Directory_Entry **m_entries;
   //  int m_size;  // # of memory module blocks this directory is responsible for
-  uint32 m_size_bytes;
-  uint32 m_size_bits;
+  uint64 m_size_bytes;
+  uint64 m_size_bits;
   int m_num_entries;
   int m_version;
 
diff --git a/src/mem/ruby/system/PerfectCacheMemory.hh b/src/mem/ruby/system/PerfectCacheMemory.hh
index 90c9273e5..6561d028b 100644
--- a/src/mem/ruby/system/PerfectCacheMemory.hh
+++ b/src/mem/ruby/system/PerfectCacheMemory.hh
@@ -43,7 +43,6 @@
 #include "mem/gems_common/Map.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/common/Address.hh"
-#include "mem/ruby/slicc_interface/AbstractChip.hh"
 
 template<class ENTRY>
 class PerfectCacheLineState {
@@ -54,11 +53,18 @@ public:
 };
 
 template<class ENTRY>
+extern inline
+ostream& operator<<(ostream& out, const PerfectCacheLineState<ENTRY>& obj)
+{
+  return out;
+}
+
+template<class ENTRY>
 class PerfectCacheMemory {
 public:
 
   // Constructors
-  PerfectCacheMemory(AbstractChip* chip_ptr);
+  PerfectCacheMemory();
 
   // Destructor
   //~PerfectCacheMemory();
@@ -106,7 +112,6 @@ private:
 
   // Data Members (m_prefix)
   Map<Address, PerfectCacheLineState<ENTRY> > m_map;
-  AbstractChip* m_chip_ptr;
 };
 
 // Output operator declaration
@@ -129,9 +134,8 @@ ostream& operator<<(ostream& out, const PerfectCacheMemory<ENTRY>& obj)
 
 template<class ENTRY>
 extern inline
-PerfectCacheMemory<ENTRY>::PerfectCacheMemory(AbstractChip* chip_ptr)
+PerfectCacheMemory<ENTRY>::PerfectCacheMemory()
 {
-  m_chip_ptr = chip_ptr;
 }
 
 // STATIC METHODS
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index dbf4dbc78..38ef09177 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -104,6 +104,9 @@ public:
   static RubyPort* getPortOnly(const string & name) {
     assert(m_ports.count(name) == 1); return m_ports[name]; }
   static RubyPort* getPort(const string & name, void (*hit_callback)(int64_t)) {
+    if (m_ports.count(name) != 1){
+      cerr << "Port " << name << " has " << m_ports.count(name) << " instances" << endl;
+    }
     assert(m_ports.count(name) == 1); m_ports[name]->registerHitCallback(hit_callback); return m_ports[name]; }
   static Network* getNetwork() { assert(m_network_ptr != NULL); return m_network_ptr; }
   static Topology* getTopology(const string & name) { assert(m_topologies.count(name) == 1); return m_topologies[name]; }
diff --git a/src/mem/ruby/system/TimerTable.cc b/src/mem/ruby/system/TimerTable.cc
index edc2de230..5d496da04 100644
--- a/src/mem/ruby/system/TimerTable.cc
+++ b/src/mem/ruby/system/TimerTable.cc
@@ -35,11 +35,9 @@
 #include "mem/ruby/system/TimerTable.hh"
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 
-TimerTable::TimerTable(Chip* chip_ptr)
+TimerTable::TimerTable()
 {
-  assert(chip_ptr != NULL);
   m_consumer_ptr  = NULL;
-  m_chip_ptr = chip_ptr;
   m_next_valid = false;
   m_next_address = Address(0);
   m_next_time = 0;
diff --git a/src/mem/ruby/system/TimerTable.hh b/src/mem/ruby/system/TimerTable.hh
index 9912036f3..eda84069d 100644
--- a/src/mem/ruby/system/TimerTable.hh
+++ b/src/mem/ruby/system/TimerTable.hh
@@ -43,13 +43,12 @@
 #include "mem/gems_common/Map.hh"
 #include "mem/ruby/common/Address.hh"
 class Consumer;
-class Chip;
 
 class TimerTable {
 public:
 
   // Constructors
-  TimerTable(Chip* chip_ptr);
+  TimerTable();
 
   // Destructor
   //~TimerTable();
@@ -77,7 +76,6 @@ private:
 
   // Data Members (m_prefix)
   Map<Address, Time> m_map;
-  Chip* m_chip_ptr;
   mutable bool m_next_valid;
   mutable Time m_next_time; // Only valid if m_next_valid is true
   mutable Address m_next_address;  // Only valid if m_next_valid is true