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authorPolina Dudnik <pdudnik@cs.wisc.edu>2009-09-17 17:39:52 -0500
committerPolina Dudnik <pdudnik@cs.wisc.edu>2009-09-17 17:39:52 -0500
commit114d8724dd5e6ff82b93b5888fcf8f99f56c0993 (patch)
tree5dd6b5607be7ad9c3b649278095d099313cf2109 /src/mem/ruby/system
parent31a3ef03cb2c991270dc2ec061b07e1e2858484c (diff)
downloadgem5-114d8724dd5e6ff82b93b5888fcf8f99f56c0993.tar.xz
Functionality migrated to sequencer.
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r--src/mem/ruby/system/Sequencer.cc77
-rw-r--r--src/mem/ruby/system/Sequencer.hh4
2 files changed, 44 insertions, 37 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 79d1955b8..bcfa0e954 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -62,8 +62,8 @@ void Sequencer::init(const vector<string> & argv)
m_instCache_ptr = NULL;
m_dataCache_ptr = NULL;
m_controller = NULL;
- m_servicing_atomic = 200;
- m_atomics_counter = 0;
+ m_atomic_reads = 0;
+ m_atomic_writes = 0;
for (size_t i=0; i<argv.size(); i+=2) {
if ( argv[i] == "controller") {
m_controller = RubySystem::getController(argv[i+1]); // args[i] = "L1Cache"
@@ -265,6 +265,7 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data) {
assert(m_writeRequestTable.exist(line_address(address)));
SequencerRequest* request = m_writeRequestTable.lookup(address);
+
removeRequest(request);
assert((request->ruby_request.type == RubyRequestType_ST) ||
@@ -280,7 +281,7 @@ void Sequencer::writeCallback(const Address& address, DataBlock& data) {
m_controller->set_atomic(address);
}
else if (request->ruby_request.type == RubyRequestType_RMW_Write) {
- m_controller->clear_atomic();
+ m_controller->clear_atomic(address);
}
hitCallback(request, data);
@@ -346,16 +347,7 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
data.setData(ruby_request.data, request_address.getOffset(), ruby_request.len);
}
}
- if (type == RubyRequestType_RMW_Write) {
- if (m_servicing_atomic != ruby_request.proc_id) {
- assert(0);
- }
- assert(m_atomics_counter > 0);
- m_atomics_counter--;
- if (m_atomics_counter == 0) {
- m_servicing_atomic = 200;
- }
- }
+
m_hit_callback(srequest->id);
delete srequest;
}
@@ -376,25 +368,6 @@ int Sequencer::isReady(const RubyRequest& request) {
return LIBRUBY_ALIASED_REQUEST;
}
- if (request.type == RubyRequestType_RMW_Read) {
- if (m_servicing_atomic == 200) {
- assert(m_atomics_counter == 0);
- m_servicing_atomic = request.proc_id;
- }
- else {
- assert(m_servicing_atomic == request.proc_id);
- }
- m_atomics_counter++;
- }
- else {
- if (m_servicing_atomic == request.proc_id) {
- if (request.type != RubyRequestType_RMW_Write) {
- m_servicing_atomic = 200;
- m_atomics_counter = 0;
- }
- }
- }
-
return 1;
}
@@ -422,9 +395,6 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
m_dataCache_ptr->clearLocked(line_address(Address(request.paddr)));
}
}
- if (request.type == RubyRequestType_RMW_Write) {
- m_controller->started_writes();
- }
issueRequest(request);
// TODO: issue hardware prefetches here
@@ -445,18 +415,55 @@ void Sequencer::issueRequest(const RubyRequest& request) {
CacheRequestType ctype;
switch(request.type) {
case RubyRequestType_IFETCH:
+ if (m_atomic_reads > 0 && m_atomic_writes == 0) {
+ m_controller->reset_atomics();
+ }
+ else if (m_atomic_writes > 0) {
+ assert(m_atomic_reads > m_atomic_writes);
+ cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
+ assert(false);
+ }
ctype = CacheRequestType_IFETCH;
break;
case RubyRequestType_LD:
+ if (m_atomic_reads > 0 && m_atomic_writes == 0) {
+ m_controller->reset_atomics();
+ }
+ else if (m_atomic_writes > 0) {
+ assert(m_atomic_reads > m_atomic_writes);
+ cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
+ assert(false);
+ }
ctype = CacheRequestType_LD;
break;
case RubyRequestType_ST:
+ if (m_atomic_reads > 0 && m_atomic_writes == 0) {
+ m_controller->reset_atomics();
+ }
+ else if (m_atomic_writes > 0) {
+ assert(m_atomic_reads > m_atomic_writes);
+ cerr << "WARNING: Expected: " << m_atomic_reads << " RMW_Writes, but only received: " << m_atomic_writes << endl;
+ assert(false);
+ }
ctype = CacheRequestType_ST;
break;
case RubyRequestType_Locked_Read:
case RubyRequestType_Locked_Write:
+ ctype = CacheRequestType_ATOMIC;
+ break;
case RubyRequestType_RMW_Read:
+ assert(m_atomic_writes == 0);
+ m_atomic_reads++;
+ ctype = CacheRequestType_ATOMIC;
+ break;
case RubyRequestType_RMW_Write:
+ assert(m_atomic_reads > 0);
+ assert(m_atomic_writes < m_atomic_reads);
+ m_atomic_writes++;
+ if (m_atomic_reads == m_atomic_writes) {
+ m_atomic_reads = 0;
+ m_atomic_writes = 0;
+ }
ctype = CacheRequestType_ATOMIC;
break;
default:
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index bdce9639a..52c7860d0 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -125,8 +125,8 @@ private:
// Global outstanding request count, across all request tables
int m_outstanding_count;
bool m_deadlock_check_scheduled;
- unsigned m_servicing_atomic;
- int m_atomics_counter;
+ int m_atomic_reads;
+ int m_atomic_writes;
};
// Output operator declaration