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authorAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-10-12 04:07:59 -0400
commit22c04190c607b9360d9a23548f8a54e83cf0e74a (patch)
tree576135962e3c9c725157b461c8009b05933bba2b /src/mem/ruby/system
parent735c4a87665119a33443cf8d191d329c66191c6e (diff)
downloadgem5-22c04190c607b9360d9a23548f8a54e83cf0e74a.tar.xz
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r--src/mem/ruby/system/CacheRecorder.hh1
-rw-r--r--src/mem/ruby/system/DMASequencer.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
-rw-r--r--src/mem/ruby/system/RubySystem.hh6
-rw-r--r--src/mem/ruby/system/Sequencer.cc6
-rw-r--r--src/mem/ruby/system/Sequencer.hh4
6 files changed, 10 insertions, 11 deletions
diff --git a/src/mem/ruby/system/CacheRecorder.hh b/src/mem/ruby/system/CacheRecorder.hh
index 44110cf9f..822b370e8 100644
--- a/src/mem/ruby/system/CacheRecorder.hh
+++ b/src/mem/ruby/system/CacheRecorder.hh
@@ -37,7 +37,6 @@
#include <vector>
-#include "base/hashmap.hh"
#include "base/types.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/ruby/common/Address.hh"
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index f9d1b630e..1d5451f6e 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -108,7 +108,7 @@ class DMASequencer : public MemObject
// A pointer to the controller is needed for atomic support.
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/* SLICC callback */
void dataCallback(const DataBlock & dblk);
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index cbcc678d3..98fab8c4e 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -161,7 +161,7 @@ class RubyPort : public MemObject
//
void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
uint32_t getId() { return m_version; }
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
protected:
void ruby_hit_callback(PacketPtr pkt);
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
index 7026f6756..23974e924 100644
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -94,9 +94,9 @@ class RubySystem : public ClockedObject
void resetStats();
void memWriteback();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
+ void drainResume() override;
void process();
void startup();
bool functionalRead(Packet *ptr);
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index aa4ac742a..26db6b6f8 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -634,10 +634,10 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
template <class KEY, class VALUE>
std::ostream &
-operator<<(ostream &out, const m5::hash_map<KEY, VALUE> &map)
+operator<<(ostream &out, const std::unordered_map<KEY, VALUE> &map)
{
- typename m5::hash_map<KEY, VALUE>::const_iterator i = map.begin();
- typename m5::hash_map<KEY, VALUE>::const_iterator end = map.end();
+ auto i = map.begin();
+ auto end = map.end();
out << "[";
for (; i != end; ++i)
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 4716aa653..47af7ea1e 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -30,8 +30,8 @@
#define __MEM_RUBY_SYSTEM_SEQUENCER_HH__
#include <iostream>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "mem/protocol/MachineType.hh"
#include "mem/protocol/RubyRequestType.hh"
#include "mem/protocol/SequencerRequestType.hh"
@@ -185,7 +185,7 @@ class Sequencer : public RubyPort
Cycles m_data_cache_hit_latency;
Cycles m_inst_cache_hit_latency;
- typedef m5::hash_map<Addr, SequencerRequest*> RequestTable;
+ typedef std::unordered_map<Addr, SequencerRequest*> RequestTable;
RequestTable m_writeRequestTable;
RequestTable m_readRequestTable;
// Global outstanding request count, across all request tables