Param: Transition to Cycles for relevant parameters

This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.

An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.

5 files changed, 7 insertions, 7 deletions

diff --git a/src/mem/ruby/system/BankedArray.cc b/src/mem/ruby/system/BankedArray.cc
index b7efa7d56..8af0701a5 100644
--- a/src/mem/ruby/system/BankedArray.cc
+++ b/src/mem/ruby/system/BankedArray.cc
@@ -36,7 +36,7 @@
 #include "mem/ruby/system/BankedArray.hh"
 #include "sim/eventq.hh"
 
-BankedArray::BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit) :
+BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit) :
     EventManager(&mainEventQueue)
 {
     this->banks = banks;
diff --git a/src/mem/ruby/system/BankedArray.hh b/src/mem/ruby/system/BankedArray.hh
index 15c2d2c15..7ebf39dfb 100644
--- a/src/mem/ruby/system/BankedArray.hh
+++ b/src/mem/ruby/system/BankedArray.hh
@@ -43,7 +43,7 @@ class BankedArray : public EventManager
 {
 private:
     unsigned int banks;
-    unsigned int accessLatency;
+    Cycles accessLatency;
     unsigned int bankBits;
     unsigned int startIndexBit;
 
@@ -66,7 +66,7 @@ private:
     unsigned int mapIndexToBank(Index idx);
 
 public:
-    BankedArray(unsigned int banks, unsigned int accessLatency, unsigned int startIndexBit);
+    BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
 
     // Note: We try the access based on the cache index, not the address
     // This is so we don't get aliasing on blocks being replaced
diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py
index 2b4daa68b..57326c3c6 100644
--- a/src/mem/ruby/system/Cache.py
+++ b/src/mem/ruby/system/Cache.py
@@ -43,6 +43,6 @@ class RubyCache(SimObject):
 
     dataArrayBanks = Param.Int(1, "Number of banks for the data array")
     tagArrayBanks = Param.Int(1, "Number of banks for the tag array")
-    dataAccessLatency = Param.Int(1, "Gem5 cycles for the data array")
-    tagAccessLatency = Param.Int(1, "Gem5 cycles for the tag array")
+    dataAccessLatency = Param.Cycles(1, "cycles for a data array access")
+    tagAccessLatency = Param.Cycles(1, "cycles for a tag array access")
     resourceStalls = Param.Bool(False, "stall if there is a resource failure")
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index dbdfca38e..cc63a93a4 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -139,7 +139,7 @@ class Sequencer : public RubyPort
 
   private:
     int m_max_outstanding_requests;
-    int m_deadlock_threshold;
+    Cycles m_deadlock_threshold;
 
     CacheMemory* m_dataCache_ptr;
     CacheMemory* m_instCache_ptr;
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 79cf9709e..deef6e714 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -58,7 +58,7 @@ class RubySequencer(RubyPort):
     dcache = Param.RubyCache("")
     max_outstanding_requests = Param.Int(16,
         "max requests (incl. prefetches) outstanding")
-    deadlock_threshold = Param.Int(500000,
+    deadlock_threshold = Param.Cycles(500000,
         "max outstanding cycles for a request before deadlock/livelock declared")
 
 class DMASequencer(RubyPort):