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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:43 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 19:28:43 -0500 |
commit | 5060e572ca07b98f7d84679bac81c0151dee46b9 (patch) | |
tree | d7ff69a0fb7c5959b038dad87cd01e08801f33fe /src/mem/ruby/system | |
parent | b815221718d246549311b2923a2da7a233e1f625 (diff) | |
download | gem5-5060e572ca07b98f7d84679bac81c0151dee46b9.tar.xz |
ruby: call setMRU from L1 controllers, not from sequencer
Currently the sequencer calls the function setMRU that updates the replacement
policy structures with the first level caches. While functionally this is
correct, the problem is that this requires calling findTagInSet() which is an
expensive function. This patch removes the calls to setMRU from the sequencer.
All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the
AbstractCacheEntry structure. Use these indicies to update the replacement
policy structures.
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r-- | src/mem/ruby/system/Sequencer.cc | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc index b21c70743..740db7d8d 100644 --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -496,19 +496,15 @@ Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data, const Cycles forwardRequestTime, const Cycles firstResponseTime) { + warn_once("Replacement policy updates recently became the responsibility " + "of SLICC state machines. Make sure to setMRU() near callbacks " + "in .sm files!"); + PacketPtr pkt = srequest->pkt; Addr request_address(pkt->getAddr()); - Addr request_line_address = makeLineAddress(pkt->getAddr()); RubyRequestType type = srequest->m_type; Cycles issued_time = srequest->issue_time; - // Set this cache entry to the most recently used - if (type == RubyRequestType_IFETCH) { - m_instCache_ptr->setMRU(request_line_address); - } else { - m_dataCache_ptr->setMRU(request_line_address); - } - assert(curCycle() >= issued_time); Cycles total_latency = curCycle() - issued_time; |