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authorAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2012-02-13 06:43:09 -0500
commit5a9a743cfc4517f93e5c94533efa767b92272c59 (patch)
treef3dbc078a51e5759b26b1a5f16263ddb1cf55a7b /src/mem/ruby/system
parent8cb4a2208d568eb86ad3f6c6bb250bcbe2952302 (diff)
downloadgem5-5a9a743cfc4517f93e5c94533efa767b92272c59.tar.xz
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
Diffstat (limited to 'src/mem/ruby/system')
-rw-r--r--src/mem/ruby/system/RubyPort.cc15
-rw-r--r--src/mem/ruby/system/Sequencer.py7
2 files changed, 17 insertions, 5 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index ab3e6e3b7..2ef65a13a 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -68,13 +68,24 @@ RubyPort::init()
Port *
RubyPort::getPort(const std::string &if_name, int idx)
{
- if (if_name == "port") {
- M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx),
+ // used by the CPUs to connect the caches to the interconnect, and
+ // for the x86 case also the interrupt master
+ if (if_name == "slave") {
+ M5Port* cpuPort = new M5Port(csprintf("%s-slave%d", name(), idx),
this, ruby_system, access_phys_mem);
cpu_ports.push_back(cpuPort);
return cpuPort;
}
+ // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
+ // port
+ if (if_name == "master") {
+ PioPort* masterPort = new PioPort(csprintf("%s-master%d", name(), idx),
+ this);
+
+ return masterPort;
+ }
+
if (if_name == "pio_port") {
// ensure there is only one pio port
assert(pio_port == NULL);
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index ddf760f7b..b1e17e052 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -34,11 +34,12 @@ from MemObject import MemObject
class RubyPort(MemObject):
type = 'RubyPort'
abstract = True
- port = VectorPort("M5 port")
+ slave = VectorSlavePort("CPU slave port")
+ master = VectorMasterPort("CPU master port")
version = Param.Int(0, "")
- pio_port = Port("Ruby_pio_port")
+ pio_port = MasterPort("Ruby_pio_port")
physmem = Param.PhysicalMemory("")
- physMemPort = Port("port to physical memory")
+ physMemPort = MasterPort("port to physical memory")
using_ruby_tester = Param.Bool(False, "")
using_network_tester = Param.Bool(False, "")
access_phys_mem = Param.Bool(True,