Change interface between coherence protocols and CacheMemory

The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.

3 files changed, 24 insertions, 68 deletions

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index e9d0d8851..b80c1c356 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -75,13 +75,10 @@ CacheMemory::init()
         assert(false);
 
     m_cache.resize(m_cache_num_sets);
-    m_locked.resize(m_cache_num_sets);
     for (int i = 0; i < m_cache_num_sets; i++) {
         m_cache[i].resize(m_cache_assoc);
-        m_locked[i].resize(m_cache_assoc);
         for (int j = 0; j < m_cache_assoc; j++) {
             m_cache[i][j] = NULL;
-            m_locked[i][j] = -1;
         }
     }
 }
@@ -255,7 +252,7 @@ CacheMemory::cacheAvail(const Address& address) const
     return false;
 }
 
-void
+AbstractCacheEntry*
 CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
 {
     assert(address == line_address(address));
@@ -273,13 +270,13 @@ CacheMemory::allocate(const Address& address, AbstractCacheEntry* entry)
             set[i]->m_Permission = AccessPermission_Invalid;
             DPRINTF(RubyCache, "Allocate clearing lock for addr: %x\n",
                     address);
-            m_locked[cacheSet][i] = -1;
+            set[i]->m_locked = -1;
             m_tag_index[address] = i;
 
             m_replacementPolicy_ptr->
                 touch(cacheSet, i, g_eventQueue_ptr->getTime());
 
-            return;
+            return entry;
         }
     }
     panic("Allocate didn't find an available entry");
@@ -296,9 +293,6 @@ CacheMemory::deallocate(const Address& address)
     if (loc != -1) {
         delete m_cache[cacheSet][loc];
         m_cache[cacheSet][loc] = NULL;
-        DPRINTF(RubyCache, "Deallocate clearing lock for addr: %x\n",
-                address);
-        m_locked[cacheSet][loc] = -1;
         m_tag_index.erase(address);
     }
 }
@@ -316,49 +310,25 @@ CacheMemory::cacheProbe(const Address& address) const
 }
 
 // looks an address up in the cache
-AbstractCacheEntry&
+AbstractCacheEntry*
 CacheMemory::lookup(const Address& address)
 {
     assert(address == line_address(address));
     Index cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
-    assert(loc != -1);
-    return *m_cache[cacheSet][loc];
+    if(loc == -1) return NULL;
+    return m_cache[cacheSet][loc];
 }
 
 // looks an address up in the cache
-const AbstractCacheEntry&
+const AbstractCacheEntry*
 CacheMemory::lookup(const Address& address) const
 {
     assert(address == line_address(address));
     Index cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
-    assert(loc != -1);
-    return *m_cache[cacheSet][loc];
-}
-
-AccessPermission
-CacheMemory::getPermission(const Address& address) const
-{
-    assert(address == line_address(address));
-    return lookup(address).m_Permission;
-}
-
-void
-CacheMemory::changePermission(const Address& address,
-                              AccessPermission new_perm)
-{
-    assert(address == line_address(address));
-    lookup(address).m_Permission = new_perm;
-    Index cacheSet = addressToCacheSet(address);
-    int loc = findTagInSet(cacheSet, address);
-    if ((new_perm == AccessPermission_Invalid) ||
-        (new_perm == AccessPermission_NotPresent) ||
-        (new_perm == AccessPermission_Stale)) {
-        DPRINTF(RubyCache, "Permission clearing lock for addr: %x\n", address);
-        m_locked[cacheSet][loc] = -1;
-    }
-    assert(getPermission(address) == new_perm);
+    if(loc == -1) return NULL;
+    return m_cache[cacheSet][loc];
 }
 
 // Sets the most recently used bit for a cache block
@@ -460,10 +430,10 @@ void
 CacheMemory::getMemoryValue(const Address& addr, char* value,
                             unsigned size_in_bytes)
 {
-    AbstractCacheEntry& entry = lookup(line_address(addr));
+    AbstractCacheEntry* entry = lookup(line_address(addr));
     unsigned startByte = addr.getAddress() - line_address(addr).getAddress();
     for (unsigned i = 0; i < size_in_bytes; ++i) {
-        value[i] = entry.getDataBlk().getByte(i + startByte);
+        value[i] = entry->getDataBlk().getByte(i + startByte);
     }
 }
 
@@ -471,11 +441,11 @@ void
 CacheMemory::setMemoryValue(const Address& addr, char* value,
                             unsigned size_in_bytes)
 {
-    AbstractCacheEntry& entry = lookup(line_address(addr));
+    AbstractCacheEntry* entry = lookup(line_address(addr));
     unsigned startByte = addr.getAddress() - line_address(addr).getAddress();
     assert(size_in_bytes > 0);
     for (unsigned i = 0; i < size_in_bytes; ++i) {
-        entry.getDataBlk().setByte(i + startByte, value[i]);
+        entry->getDataBlk().setByte(i + startByte, value[i]);
     }
 
     // entry = lookup(line_address(addr));
@@ -489,7 +459,7 @@ CacheMemory::setLocked(const Address& address, int context)
     Index cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
-    m_locked[cacheSet][loc] = context;
+    m_cache[cacheSet][loc]->m_locked = context;
 }
 
 void
@@ -500,7 +470,7 @@ CacheMemory::clearLocked(const Address& address)
     Index cacheSet = addressToCacheSet(address);
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
-    m_locked[cacheSet][loc] = -1;
+    m_cache[cacheSet][loc]->m_locked = -1;
 }
 
 bool
@@ -511,7 +481,7 @@ CacheMemory::isLocked(const Address& address, int context)
     int loc = findTagInSet(cacheSet, address);
     assert(loc != -1);
     DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n",
-            address, m_locked[cacheSet][loc], context);
-    return m_locked[cacheSet][loc] == context;
+            address, m_cache[cacheSet][loc]->m_locked, context);
+    return m_cache[cacheSet][loc]->m_locked == context;
 }
 
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 3ef951821..1f0ffd500 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -82,7 +82,7 @@ class CacheMemory : public SimObject
     bool cacheAvail(const Address& address) const;
 
     // find an unused entry and sets the tag appropriate for the address
-    void allocate(const Address& address, AbstractCacheEntry* new_entry);
+    AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
 
     // Explicitly free up this address
     void deallocate(const Address& address);
@@ -91,12 +91,8 @@ class CacheMemory : public SimObject
     Address cacheProbe(const Address& address) const;
 
     // looks an address up in the cache
-    AbstractCacheEntry& lookup(const Address& address);
-    const AbstractCacheEntry& lookup(const Address& address) const;
-
-    // Get/Set permission of cache block
-    AccessPermission getPermission(const Address& address) const;
-    void changePermission(const Address& address, AccessPermission new_perm);
+    AbstractCacheEntry* lookup(const Address& address);
+    const AbstractCacheEntry* lookup(const Address& address) const;
 
     int getLatency() const { return m_latency; }
 
@@ -158,7 +154,6 @@ class CacheMemory : public SimObject
     // The second index is the the amount associativity.
     m5::hash_map<Address, int> m_tag_index;
     std::vector<std::vector<AbstractCacheEntry*> > m_cache;
-    std::vector<std::vector<int> > m_locked;
 
     AbstractReplacementPolicy *m_replacementPolicy_ptr;
 
diff --git a/src/mem/ruby/system/TBETable.hh b/src/mem/ruby/system/TBETable.hh
index da33cc9d2..022654bce 100644
--- a/src/mem/ruby/system/TBETable.hh
+++ b/src/mem/ruby/system/TBETable.hh
@@ -61,8 +61,7 @@ class TBETable
         return (m_number_of_TBEs - m_map.size()) >= n;
     }
 
-    ENTRY& lookup(const Address& address);
-    const ENTRY& lookup(const Address& address) const;
+    ENTRY* lookup(const Address& address);
 
     // Print cache contents
     void print(std::ostream& out) const;
@@ -117,21 +116,13 @@ TBETable<ENTRY>::deallocate(const Address& address)
 
 // looks an address up in the cache
 template<class ENTRY>
-inline ENTRY&
+inline ENTRY*
 TBETable<ENTRY>::lookup(const Address& address)
 {
-    assert(isPresent(address));
-    return m_map.find(address)->second;
+  if(m_map.find(address) != m_map.end()) return &(m_map.find(address)->second);
+  return NULL;
 }
 
-// looks an address up in the cache
-template<class ENTRY>
-inline const ENTRY&
-TBETable<ENTRY>::lookup(const Address& address) const
-{
-    assert(isPresent(address));
-    return m_map.find(address)->second;
-}
 
 template<class ENTRY>
 inline void