ruby: enable multiple clock domains

This patch allows ruby to have multiple clock domains. As I understand
with this patch, controllers can have different frequencies. The entire
network needs to run at a single frequency.

The idea is that with in an object, time is treated in terms of cycles.
But the messages that are passed from one entity to another should contain
the time in Ticks. As of now, this is only true for the message buffers,
but not for the links in the network. As I understand the code, all the
entities in different networks (simple, garnet-fixed, garnet-flexible) should
be clocked at the same frequency.

Another problem is that the directory controller has to operate at the same
frequency as the ruby system. This is because the memory controller does
not make use of the Message Buffer, and instead implements a buffer of its
own. So, it has no idea of the frequency at which the directory controller
is operating and uses ruby system's frequency for scheduling events.

7 files changed, 10 insertions, 11 deletions

diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index fe9ab39be..37df1c653 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -70,7 +70,7 @@ DMASequencer::makeRequest(PacketPtr pkt)
     active_request.bytes_issued = 0;
     active_request.pkt = pkt;
 
-    SequencerMsg *msg = new SequencerMsg(curCycle());
+    SequencerMsg *msg = new SequencerMsg(clockEdge());
     msg->getPhysicalAddress() = Address(paddr);
     msg->getLineAddress() = line_address(msg->getPhysicalAddress());
     msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
@@ -108,7 +108,7 @@ DMASequencer::issueNext()
         return;
     }
 
-    SequencerMsg *msg = new SequencerMsg(curCycle());
+    SequencerMsg *msg = new SequencerMsg(clockEdge());
     msg->getPhysicalAddress() = Address(active_request.start_paddr +
                                        active_request.bytes_completed);
 
diff --git a/src/mem/ruby/system/RubyMemoryControl.cc b/src/mem/ruby/system/RubyMemoryControl.cc
index 542835102..6212f049c 100644
--- a/src/mem/ruby/system/RubyMemoryControl.cc
+++ b/src/mem/ruby/system/RubyMemoryControl.cc
@@ -278,7 +278,7 @@ RubyMemoryControl::~RubyMemoryControl()
 void
 RubyMemoryControl::enqueue(const MsgPtr& message, Cycles latency)
 {
-    Cycles arrival_time = g_system_ptr->getTime() + latency;
+    Cycles arrival_time = curCycle() + latency;
     const MemoryMsg* memMess = safe_cast<const MemoryMsg*>(message.get());
     physical_address_t addr = memMess->getAddress().getAddress();
     MemoryRequestType type = memMess->getType();
@@ -345,7 +345,7 @@ bool
 RubyMemoryControl::isReady()
 {
     return ((!m_response_queue.empty()) &&
-            (m_response_queue.front().m_time <= g_system_ptr->getTime()));
+            (m_response_queue.front().m_time <= g_system_ptr->curCycle()));
 }
 
 void
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index dd9e9676e..2f1cc622d 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -76,6 +76,7 @@ RubyPort::init()
 {
     assert(m_controller != NULL);
     m_mandatory_q_ptr = m_controller->getMandatoryQueue();
+    m_mandatory_q_ptr->setSender(this);
 }
 
 BaseMasterPort &
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 98bcede44..cec356edb 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -46,13 +46,13 @@
 #include <string>
 
 #include "mem/protocol/RequestStatus.hh"
+#include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/system/System.hh"
 #include "mem/mem_object.hh"
 #include "mem/physical.hh"
 #include "mem/tport.hh"
 #include "params/RubyPort.hh"
 
-class MessageBuffer;
 class AbstractController;
 
 class RubyPort : public MemObject
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 94ad42d9d..1cdd6d806 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -39,7 +39,6 @@
 #include "debug/RubyStats.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/protocol/RubyAccessMode.hh"
-#include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/common/Global.hh"
 #include "mem/ruby/profiler/Profiler.hh"
 #include "mem/ruby/slicc_interface/RubyRequest.hh"
@@ -657,7 +656,7 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
         pc = pkt->req->getPC();
     }
 
-    RubyRequest *msg = new RubyRequest(curCycle(), pkt->getAddr(),
+    RubyRequest *msg = new RubyRequest(clockEdge(), pkt->getAddr(),
                                        pkt->getPtr<uint8_t>(true),
                                        pkt->getSize(), pc, secondary_type,
                                        RubyAccessMode_Supervisor, pkt,
diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh
index f07303cf4..1e0be6da7 100644
--- a/src/mem/ruby/system/System.hh
+++ b/src/mem/ruby/system/System.hh
@@ -79,7 +79,6 @@ class RubySystem : public ClockedObject
     static uint32_t getBlockSizeBits() { return m_block_size_bits; }
     static uint64_t getMemorySizeBytes() { return m_memory_size_bytes; }
     static uint32_t getMemorySizeBits() { return m_memory_size_bits; }
-    Cycles getTime() const { return curCycle(); }
 
     // Public Methods
     Network*
diff --git a/src/mem/ruby/system/WireBuffer.cc b/src/mem/ruby/system/WireBuffer.cc
index fba53b902..e0458550a 100644
--- a/src/mem/ruby/system/WireBuffer.cc
+++ b/src/mem/ruby/system/WireBuffer.cc
@@ -73,7 +73,7 @@ void
 WireBuffer::enqueue(MsgPtr message, Cycles latency)
 {
     m_msg_counter++;
-    Cycles current_time = g_system_ptr->getTime();
+    Cycles current_time = g_system_ptr->curCycle();
     Cycles arrival_time = current_time + latency;
     assert(arrival_time > current_time);
 
@@ -124,7 +124,7 @@ WireBuffer::recycle()
     pop_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
 
-    node.m_time = g_system_ptr->getTime() + Cycles(1);
+    node.m_time = g_system_ptr->curCycle() + Cycles(1);
     m_message_queue.back() = node;
     push_heap(m_message_queue.begin(), m_message_queue.end(),
         greater<MessageBufferNode>());
@@ -135,7 +135,7 @@ bool
 WireBuffer::isReady()
 {
     return ((!m_message_queue.empty()) &&
-            (m_message_queue.front().m_time <= g_system_ptr->getTime()));
+            (m_message_queue.front().m_time <= g_system_ptr->curCycle()));
 }
 
 void