Ruby: Convert CacheRequestType to RubyRequestType

This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.

5 files changed, 22 insertions, 30 deletions

diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index 7fcb5431b..ea5054e4c 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -159,7 +159,7 @@ CacheMemory::findTagInSetIgnorePermissions(Index cacheSet,
 }
 
 bool
-CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
+CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type,
                             DataBlock*& data_ptr)
 {
     assert(address == line_address(address));
@@ -177,7 +177,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
             return true;
         }
         if ((entry->m_Permission == AccessPermission_Read_Only) &&
-            (type == CacheRequestType_LD || type == CacheRequestType_IFETCH)) {
+            (type == RubyRequestType_LD || type == RubyRequestType_IFETCH)) {
             return true;
         }
         // The line must not be accessible
@@ -187,7 +187,7 @@ CacheMemory::tryCacheAccess(const Address& address, CacheRequestType type,
 }
 
 bool
-CacheMemory::testCacheAccess(const Address& address, CacheRequestType type,
+CacheMemory::testCacheAccess(const Address& address, RubyRequestType type,
                              DataBlock*& data_ptr)
 {
     assert(address == line_address(address));
@@ -367,18 +367,18 @@ CacheMemory::recordCacheContents(CacheRecorder& tr) const
     for (int i = 0; i < m_cache_num_sets; i++) {
         for (int j = 0; j < m_cache_assoc; j++) {
             AccessPermission perm = m_cache[i][j]->m_Permission;
-            CacheRequestType request_type = CacheRequestType_NULL;
+            RubyRequestType request_type = RubyRequestType_NULL;
             if (perm == AccessPermission_Read_Only) {
                 if (m_is_instruction_only_cache) {
-                    request_type = CacheRequestType_IFETCH;
+                    request_type = RubyRequestType_IFETCH;
                 } else {
-                    request_type = CacheRequestType_LD;
+                    request_type = RubyRequestType_LD;
                 }
             } else if (perm == AccessPermission_Read_Write) {
-                request_type = CacheRequestType_ST;
+                request_type = RubyRequestType_ST;
             }
 
-            if (request_type != CacheRequestType_NULL) {
+            if (request_type != RubyRequestType_NULL) {
 #if 0
                 tr.addRecord(m_chip_ptr->getID(), m_cache[i][j].m_Address,
                              Address(0), request_type,
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 6e311edc3..4e7acd4ec 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -36,7 +36,7 @@
 #include "base/hashmap.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/protocol/CacheMsg.hh"
-#include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/common/Address.hh"
@@ -66,11 +66,11 @@ class CacheMemory : public SimObject
     void printConfig(std::ostream& out);
 
     // perform a cache access and see if we hit or not.  Return true on a hit.
-    bool tryCacheAccess(const Address& address, CacheRequestType type,
+    bool tryCacheAccess(const Address& address, RubyRequestType type,
                         DataBlock*& data_ptr);
 
     // similar to above, but doesn't require full access check
-    bool testCacheAccess(const Address& address, CacheRequestType type,
+    bool testCacheAccess(const Address& address, RubyRequestType type,
                          DataBlock*& data_ptr);
 
     // tests to see if an address is present in the cache
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index e8e279043..772bc5142 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -64,15 +64,7 @@ DMASequencer::makeRequest(const RubyRequest &request)
       case RubyRequestType_ST:
         write = true;
         break;
-      case RubyRequestType_NULL:
-      case RubyRequestType_IFETCH:
-      case RubyRequestType_Load_Linked:
-      case RubyRequestType_Store_Conditional:
-      case RubyRequestType_RMW_Read:
-      case RubyRequestType_RMW_Write:
-      case RubyRequestType_Locked_RMW_Read:
-      case RubyRequestType_Locked_RMW_Write:
-      case RubyRequestType_NUM:
+      default:
         panic("DMASequencer::makeRequest does not support RubyRequestType");
         return RequestStatus_NULL;
     }
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 7f916957b..6b0f6e49f 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -604,16 +604,16 @@ Sequencer::makeRequest(const RubyRequest &request)
 void
 Sequencer::issueRequest(const RubyRequest& request)
 {
-    // TODO: get rid of CacheMsg, CacheRequestType, and
+    // TODO: get rid of CacheMsg, RubyRequestType, and
     // AccessModeTYpe, & have SLICC use RubyRequest and subtypes
     // natively
-    CacheRequestType ctype;
+    RubyRequestType ctype;
     switch(request.type) {
       case RubyRequestType_IFETCH:
-        ctype = CacheRequestType_IFETCH;
+        ctype = RubyRequestType_IFETCH;
         break;
       case RubyRequestType_LD:
-        ctype = CacheRequestType_LD;
+        ctype = RubyRequestType_LD;
         break;
       case RubyRequestType_ST:
       case RubyRequestType_RMW_Read:
@@ -626,7 +626,7 @@ Sequencer::issueRequest(const RubyRequest& request)
       //
       case RubyRequestType_Locked_RMW_Read:
       case RubyRequestType_Locked_RMW_Write:
-        ctype = CacheRequestType_ST;
+        ctype = RubyRequestType_ST;
         break;
       //
       // Alpha LL/SC instructions need to be handled carefully by the cache
@@ -638,7 +638,7 @@ Sequencer::issueRequest(const RubyRequest& request)
       //
       case RubyRequestType_Load_Linked:
       case RubyRequestType_Store_Conditional:
-        ctype = CacheRequestType_ATOMIC;
+        ctype = RubyRequestType_ATOMIC;
         break;
       default:
         assert(0);
@@ -685,12 +685,12 @@ Sequencer::issueRequest(const RubyRequest& request)
 
 #if 0
 bool
-Sequencer::tryCacheAccess(const Address& addr, CacheRequestType type,
+Sequencer::tryCacheAccess(const Address& addr, RubyRequestType type,
                           RubyAccessMode access_mode,
                           int size, DataBlock*& data_ptr)
 {
     CacheMemory *cache =
-        (type == CacheRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
+        (type == RubyRequestType_IFETCH) ? m_instCache_ptr : m_dataCache_ptr;
 
     return cache->tryCacheAccess(line_address(addr), type, data_ptr);
 }
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 7793af889..14b6997e8 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -33,7 +33,7 @@
 
 #include "base/hashmap.hh"
 #include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/CacheRequestType.hh"
+#include "mem/protocol/RubyRequestType.hh"
 #include "mem/protocol/GenericMachineType.hh"
 #include "mem/protocol/PrefetchBit.hh"
 #include "mem/ruby/common/Address.hh"
@@ -112,7 +112,7 @@ class Sequencer : public RubyPort, public Consumer
     void removeRequest(SequencerRequest* request);
 
   private:
-    bool tryCacheAccess(const Address& addr, CacheRequestType type,
+    bool tryCacheAccess(const Address& addr, RubyRequestType type,
                         const Address& pc, RubyAccessMode access_mode,
                         int size, DataBlock*& data_ptr);
     void issueRequest(const RubyRequest& request);