O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs

This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.

This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.

1 files changed, 4 insertions, 1 deletions

diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index a6eb4d22d..c829bf66e 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -41,6 +41,7 @@
 
 #include "cpu/testers/rubytest/RubyTester.hh"
 #include "debug/Config.hh"
+#include "debug/Drain.hh"
 #include "debug/Ruby.hh"
 #include "mem/protocol/AccessPermission.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
@@ -524,8 +525,9 @@ RubyPort::testDrainComplete()
     //If we weren't able to drain before, we might be able to now.
     if (drainEvent != NULL) {
         unsigned int drainCount = getDrainCount(drainEvent);
-        DPRINTF(Config, "Drain count: %u\n", drainCount);
+        DPRINTF(Drain, "Drain count: %u\n", drainCount);
         if (drainCount == 0) {
+            DPRINTF(Drain, "RubyPort done draining, processing drain event\n");
             drainEvent->process();
             // Clear the drain event once we're done with it.
             drainEvent = NULL;
@@ -584,6 +586,7 @@ RubyPort::drain(Event *de)
     if (count != 0) {
         drainEvent = de;
 
+        DPRINTF(Drain, "RubyPort not drained\n");
         changeState(SimObject::Draining);
         return count;
     }